一个verilog 的位宽限定问题

testbench里面的验证情况应该是thetaErrfix = ThetaErr
但是如果判断条件里面用16'd2047来比较，就得不到正确结果，
如果去掉16’d的限制，直接用2047来比较，结果就是正确的。
谁能给个解释，谢谢。
module deltatheta_fix (
                  input wire clk,
                  input wire rst_n,
                  input wire en,
            input wire signed [15:0] ThetaErr,
            output reg signed [15:0]  ThetaErrFix,
            output reg DeltaThetaFix_Done
                  
                                        );
          always @(posedge clk)
          begin:ThetaErrFix_Block
            if (!rst_n) begin
              ThetaErrFix <= 'b0;
            end
            else if (ThetaErr >= 16'd2047) begin  ----这里的16'd
              ThetaErrFix <= ThetaErr - 16'd4096;
            end
            else if (ThetaErr  < -16'd2047) begin -----这里的16'd
              ThetaErrFix <= ThetaErr + 16'd4096;
            end
            else begin
              ThetaErrFix <= ThetaErr;
            end
          end
          always @(posedge clk)
          begin:DeltaThetaFix_Done_block
            if (!rst_n) begin
              DeltaThetaFix_Done <= 1'b0;
            end
            else begin
              DeltaThetaFix_Done <= en;
            end
          end
endmodule
module test_deltatheta_fix ;
parameter CLOCK_PERIOD=30;
reg clk;
reg en;
reg signed[15:0] ThetaErr;
wire signed[15:0] ThetaErrFix;
wire DeltaThetaFix_Done;
reg rst_n;
     deltatheta_fix M_1  (
                         .clk(clk),
             .rst_n(rst_n),
             .en(en),
             .ThetaErr(ThetaErr),
             .ThetaErrFix(ThetaErrFix),
             .DeltaThetaFix_Done(DeltaThetaFix_Done)
                 );
initial
        begin
     T_INIT;
     en = 1;
     ThetaErr = -700;
                 T_RESET;
     repeat(10) begin
       #(10*CLOCK_PERIOD) ThetaErr = ThetaErr + 1;
     end
     $stop;
                 #(50000 * CLOCK_PERIOD)$stop;
        end                                                                            
always
        begin:clock_gen_block
                #(CLOCK_PERIOD/2) clk <= !clk;  
        end                                                                    
  
task T_INIT;
  begin
   clk <= 1'b0;
     rst_n <= 1'b1;
  end
endtask
task T_RESET;
        begin
      rst_n <= 1'b0;
      #(2.2*CLOCK_PERIOD) rst_n <= 1'b1;
        end
endtask
endmodule