a question about SystemVerilog randomize
时间:12-12
整理:3721RD
点击:
sorry, I can't type Chinese.
below is one segment of my code:
"
class cfg_mc_c extends cfg_base_c;
//public properties
typedef enum {LONG=0, SHORT=1, NONE=2} DLY_TP;
rand DLY_TP rw_delay_type;
rand int unsigned rw_delay_max; //ns
rand int unsigned rw_delay_min;
rand int unsigned rw_delay;
//empty test constraints
constraint c_test1;
constraint c_test2;
constraint c_test3;
//defined constraints
constraint c_type2range {
if (rw_delay_type == LONG) {
rw_delay_max == 200;
rw_delay_min == 100;
}
else if (rw_delay_type == SHORT) {
rw_delay_max == 50;
rw_delay_min == 10;
}
else {
rw_delay_max == 0;
rw_delay_min == 0;
}
}
constraint c_range2delay {
rw_delay inside {[rw_delay_min:rw_delay_max]};
}
"
my intention is:
1. if the tester DOESN'T specify the rw_delay_type, then all of the variable will be randomized according to the constraint;
2. if the tester specify the rw_delay_type, then the variables except "rw_delay_type" will be randomized according to the constraints.
there is no problem with 1. but if I want to specify the rw_delay_type by below means:
"
env.cfg.mc.rw_delay_type.rand_mode(0); //disable the random for dly_tp
env.cfg.mc.rw_delay_type = 1; //specify the value for dly_tp
"
such error message I got:
"
Error-[CNST-CIF] Constraints inconsistency failure
/proj/xxxx/data/rave/shared/private/mc_model_c.sv, 132
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
"
Help me PLEASE
below is one segment of my code:
"
class cfg_mc_c extends cfg_base_c;
//public properties
typedef enum {LONG=0, SHORT=1, NONE=2} DLY_TP;
rand DLY_TP rw_delay_type;
rand int unsigned rw_delay_max; //ns
rand int unsigned rw_delay_min;
rand int unsigned rw_delay;
//empty test constraints
constraint c_test1;
constraint c_test2;
constraint c_test3;
//defined constraints
constraint c_type2range {
if (rw_delay_type == LONG) {
rw_delay_max == 200;
rw_delay_min == 100;
}
else if (rw_delay_type == SHORT) {
rw_delay_max == 50;
rw_delay_min == 10;
}
else {
rw_delay_max == 0;
rw_delay_min == 0;
}
}
constraint c_range2delay {
rw_delay inside {[rw_delay_min:rw_delay_max]};
}
"
my intention is:
1. if the tester DOESN'T specify the rw_delay_type, then all of the variable will be randomized according to the constraint;
2. if the tester specify the rw_delay_type, then the variables except "rw_delay_type" will be randomized according to the constraints.
there is no problem with 1. but if I want to specify the rw_delay_type by below means:
"
env.cfg.mc.rw_delay_type.rand_mode(0); //disable the random for dly_tp
env.cfg.mc.rw_delay_type = 1; //specify the value for dly_tp
"
such error message I got:
"
Error-[CNST-CIF] Constraints inconsistency failure
/proj/xxxx/data/rave/shared/private/mc_model_c.sv, 132
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
"
Help me PLEASE
如果你想指定的话,不用rand_mode(0)也可以啊,直接.randomize with {...=1;}不就行了
另外,有依赖关系的约束大概 加上solve...before比较好,你两个约束块都加上这个试试
将
env.cfg.mc.rw_delay_type.rand_mode(0); //disable the random for dly_tp
env.cfg.mc.rw_delay_type = 1; //specify the value for dly_tp
改为
env.cfg.mc.randomize_with {delay_type == cfg_mc_c::SINGLE};