一个关于等价验证的问题
时间：12-11
整理：3721RD
点击：
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xcoco (从来就是这样酷...) 于 (Wed Aug 24 16:05:36 2005) 提到:
从网上下了一个电路的verilog逻辑网表，用DC综合了一下，一切正常，可在等价性检查时却报告两个电路的很多输出端都不等价，为什么呢？如果综合出来的电路和原设计功能都不一样，那还作什么啊？问题出在哪里？
等价验证用的是Prover的echeck，是基于形式验证的。
谢谢
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QArk (SapphireSequenceDesign) 于 (Wed Aug 24 16:09:20 2005) 提到:
可能有COT吧，把LOG 文件传上来看看
【 在 xcoco (从来就是这样酷...) 的大作中提到: 】
: 从网上下了一个电路的verilog逻辑网表，用DC综合了一下，一切正常，可在等价性检查时却报告两个电路的很多输出端都不等价，为什么呢？如果综合出来的电路和原设计功能都不一样，那还作什么啊？问题出在哪里？
: 等价验证用的是Prover的echeck，是基于形式验证的。
: 谢谢
: ...................
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xcoco (从来就是这样酷...) 于 (Wed Aug 24 18:39:09 2005) 提到:
COT？不太明白，你是说我用了自己的库？我用的是dc的10k的库，而且还没做constraint，实在不明白哪里出了问题。下面是dc的log
#@ #
#@ # Running dc_shell Version 2000.05-1 -- Jul 12, 2000
#@ # Date: Wed Aug 24 14:34:55 2005
#@
source e:/Synopsys/admin/setup/.synopsys_dc.setup
#@ #
#@ #
#@ # ".synopsys_dc.setup" Initialization File for
#@ #
#@ # Dc_Shell and Design_Analyzer
#@ #
#@ # The variables in this file define the behavior of many parts
#@ # of the Synopsys Synthesis Tools. Upon installation, they should
#@ # be reviewed and modified to fit your site's needs. Each engineer
#@ # can have a .synopsys file in his/her home directory or current
#@ # directory to override variable settings in this file.
#@ #
#@ # Each logical grouping of variables is commented as to their
#@ # nature and effect on the Synthesis Commands. Examples of
#@ # variable groups are the Compile Variable Group, which affects
#@ # the designs produced by the COMPILE command, and the Schematic
#@ # Variable Group, which affects the output of the create_schematic
#@ # command.
#@ #
#@ # You can type "man <group_name>_variables" in dc_shell or
#@ # design_analyzer to get help about a group of variables.
#@ # For instance, to get help about the "system" variable group,
#@ # type "help system_variables". You can also type
#@ # "man <variable name>", to get help on the that variable's
#@ # group.
#@ #
#@
#@ # System variables
#@ set sh_command_abbrev_mode "Anywhere"
#@ set sh_continue_on_error "true"
#@ set sh_enable_page_mode "true"
#@ set sh_source_uses_search_path "true"
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ set sh_command_log_file "./command.log"
#@ }
#@
#@
#@
#@ # Enable debug output on fatal
#@ if { ( ( ( $sh_arch == {sparc}) || ( $sh_arch == {sparcOS5})) || ( $sh_arch == {hp700})) || ( $sh_arch == {hpux10}) } {
#@ setenv SYNOPSYS_TRACE {}
#@ }
#@
#@ #
#@ # Load the procedures which make up part of the user interface.
#@ #
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl
#@ source $synopsys_root/auxx/syn/.dc_procs.tcl
#@ alias list_commands help
#@ }
#@ ##############################################################################
#@ #
#@ #
#@ # FILE: auxx/syn/.dc_common_procs.tcl
#@ #
#@ # ABSTRACT: These procedures are part of the PrimeTime and DC
#@ # user interface.
#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup.
#@ #
#@ ##############################################################################
#@ #
#@ #
#@
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: group_variable
#@ #
#@ # ABSTRACT: Add a variable to the specified variable group.
#@ # This command is typically used by the system
#@ # administrator only.
#@ #
#@ # Below the proc is the command which creates the command
#@ # help information and semantic data for the argument.
#@ #
#@ # RETURNS: 1 if it is successful.
#@ # error code if the variable does not exist.
#@ # error code of the variable is already in the group.
#@ #
#@ # SYNTAX: group_variable group_name variable_name
#@ #
#@ ##############################################################################
#@ #
#@
#@
#@ proc group_variable { args } {
#@ global _Variable_Groups
#@
#@ parse_proc_arguments -args $args resarr
#@ set group $resarr(group)
#@ set var $resarr(variable_name)
#@
#@ if { ![info exists _Variable_Groups($group)] } {
#@ set _Variable_Groups($group) ""
#@ }
#@
#@ # Verify that var exists as a global variable
#@
#@ set cmd "uplevel #0 \{info exists $var\}"
#@ if { ![eval $cmd] } {
#@ return -code error "Variable '$var' is not defined."
#@ }
#@
#@ # Only add it if it's not already there
#@
#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } {
#@ lappend _Variable_Groups($group) $var
#@ }
#@
#@ return 1
#@ }
#@
#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args {
#@ {group "Variable group name" group}
#@ {variable_name "Variable name" variable_name}}
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: print_variable_group
#@ #
#@ # ABSTRACT: Shows variables and their values defined in the given group.
#@
#@ #
#@ # Below the proc is the command which creates the command
#@ # help information and semantic data for the argument.
#@ #
#@ # RETURNS: 1 if it is successful.
#@ # error code of the variable group does not exist.
#@ #
#@ # SYNTAX: print_variable_group group_name
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc print_variable_group { args } {
#@ global _Variable_Groups
#@
#@ parse_proc_arguments -args $args resarr
#@ set group $resarr(group)
#@
#@ if { [string compare $group "all"] == 0 } {
#@ set cmd "uplevel #0 \{printvar\}"
#@ return [eval $cmd]
#@ }
#@
#@ if { ![info exists _Variable_Groups($group)] } {
#@ return -code error "Variable group '$group' does not exist."
#@ }
#@
#@ # Print out each global variable in the list. To be totally bulletproof,
#@ # test that each variable in the group is still defined. If not, remove
#@ # it from the list.
#@
#@ foreach var [lsort $_Variable_Groups($group)] {
#@ set cmd "uplevel #0 \{info exists $var\}"
#@ if { ![eval $cmd] } {
#@ # Remove it
#@ set n [lsearch $_Variable_Groups($group) $var]
#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n]
#@ } else {
#@ # Print it.
#@ set cmd "uplevel #0 \{set $var\}"
#@ set val [eval $cmd]
#@ echo [format "%-25s = \"%s\"" $var $val]
#@ }
#@ }
#@
#@ return 1
#@ }
#@
#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}}
#@
#@ # -- End source e:/Synopsys/auxx/syn/.dc_common_procs.tcl
#@ ##############################################################################
#@ #
#@ #
#@ # FILE: auxx/syn/.dc_procs.tcl
#@ #
#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl
#@ # user interface.
#@ # They are loaded by .synopsys_dc.setup.
#@ #
#@ ##############################################################################
#@ #
#@ #
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_verilog
#@ #
#@ # ABSTRACT: Emulate PT's read_verilog command in DC:
#@ #
#@ # Usage: read_verilog # Read one or more verilog files
#@ # *[-hdl_compiler] (Use HDL Compiler (ignored))
#@ # file_names (Files to read)
#@ #
#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command
#@ # sees user/hidden variables from the top level. Star 92970.
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc read_verilog { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format verilog [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}
#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}}
#@ }
#@
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_vhdl
#@ #
#@ # ABSTRACT: Emulate PT's read_vhdl command in DC:
#@ #
#@ # Usage: read_vhdl # Read one or more vhdl files
#@ # file_names (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc read_vhdl { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format vhdl [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}}
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_db
#@ #
#@ # ABSTRACT: Emulate PT's read_db command in DC:
#@ #
#@ # Usage:
#@ # read_db # Read one or more db files
#@ # *[-netlist_only] (Do not read any attributes from db (ignored))
#@ # *[-library] (File is a library DB (ignored))
#@ # file_names (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc read_db { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}
#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}}
#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}}
#@ }
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_edif
#@ #
#@ # ABSTRACT: Emulate PT's read_edif command in DC:
#@ #
#@ # Usage:
#@ # read_edif # Read one or more edif files
#@ # *[-complete_language] (Use ptxr to read the file (ignored))
#@ # file_names (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@ proc read_edif { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}
#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}}
#@ }
#@
#@ # -- End source e:/Synopsys/auxx/syn/.dc_procs.tcl
#@
#@ # Temporary fix for the LMC_HOME variable- set it to an empty string
#@
#@ if { [catch {getenv LMC_HOME } __err ] != 0 } {
#@ setenv LMC_HOME ""
#@ }
#@
#@
#@ #
#@ #
#@ # Site-Specific Variables
#@ #
#@ # These are the variables that are most commonly changed at a
#@ # specific site, either upon installation of the Synopsys software,
#@ # or by specific engineers in their local .synopsys files.
#@ #
#@ #
#@
#@ # from the System Variable Group
#@ set link_force_case "check_reference"
#@ set link_library { * your_library.db }
#@
#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/dw/sim_ver]
#@ set target_library your_library.db
#@ set synthetic_library ""
#@ set command_log_file "./command.log"
#@ set designer ""
#@ set company ""
#@ set find_converts_name_lists "false"
#@
#@ set symbol_library your_library.sdb
#@
#@ # from the Schematic Variable Group
#@
#@ # from the Plot Variable Group
#@ if { $sh_arch == "hp700" } {
#@ set plot_command "lp -d"
#@ } else {
#@ set plot_command "lpr -Plw"
#@ }
#@
#@ set view_command_log_file "./view_command.log"
#@
#@ # from the View Variable group
#@ if { $sh_arch == "hp700" } {
#@ set text_print_command "lp -d"
#@ } else {
#@ set text_print_command "lpr -Plw"
#@ }
#@ #
#@ # System Variable Group:
#@ #
#@ # These variables are system-wide variables.
#@ #
#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid
#@ set auto_link_disable "false"
#@ set auto_link_options "-all"
#@ set uniquify_naming_style "%s_%d"
#@ set verbose_messages "true"
#@ set echo_include_commands "true"
#@ set preserve_subshells "hdl_shell_exec"
#@ set suppress_errors {PWR-18 OPT-931 OPT-932}
#@ set change_names_update_inst_tree "true"
#@ set change_names_dont_change_bus_members false
#@ set default_name_rules ""
#@
#@ #
#@ # Compile Variable Group:
#@ #
#@ # These variables affect the designs created by the COMPILE command.
#@ #
#@ set compile_assume_fully_decoded_three_state_busses "false"
#@ set compile_automatic_clock_phase_inference "strict"
#@ set compile_no_new_cells_at_top_level "false"
#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false"
#@ set compile_update_annotated_delays_during_inplace_opt "true"
#@ set compile_instance_name_prefix "U"
#@ set compile_instance_name_suffix ""
#@ set compile_negative_logic_methodology "false"
#@ set compile_disable_hierarchical_inverter_opt "false"
#@ set compile_use_fast_delay_mode "true"
#@ set compile_use_low_timing_effort "false"
#@ set compile_new_boolean_structure "false"
#@ set compile_fix_cell_degradation "false"
#@ set compile_preserve_subdesign_interfaces "false"
#@ set compile_sequential_area_recovery "false"
#@ set port_complement_naming_style "%s_BAR"
#@ set compile_implementation_selection "true"
#@ set compile_mux_no_boundary_optimization "false"
#@ set compile_create_mux_op_hierarchy "true"
#@ set compile_delete_unloaded_sequential_cells "true"
#@ set reoptimize_design_changed_list_file_name ""
#@ set compile_checkpoint_filename "./CHECKPOINT.db"
#@ set compile_checkpoint_cpu_interval 0.0
#@ set compile_checkpoint_phases "false"
#@ set compile_checkpoint_pre_delay_filename "./CHECKPOINT_PRE_DELAY.db"
#@ set compile_checkpoint_pre_drc1_filename "./CHECKPOINT_PRE_DRC1.db"
#@ set compile_checkpoint_pre_drc2_filename "./CHECKPOINT_PRE_DRC2.db"
#@ set compile_checkpoint_pre_area_filename "./CHECKPOINT_PRE_AREA.db"
#@ set compile_cpu_limit 0.0
#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint";
#@ set compile_top_all_paths "false"
#@ set default_port_connection_class "universal"
#@ set compile_dw_simple_mode "false"
#@ set compile_simple_mode_block_effort "none"
#@ set compile_hold_reduce_cell_count "false"
#@
#@
#@ set ldd_return_val 0
#@ if { [string compare $dc_shell_mode "default"] == 0 } {
#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh
#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val "
#@
#@ }
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl
#@ alias list_duplicate_designs "source $ldd_script; set dc_shell_status $ldd_return_val "
#@ }
#@
#@
#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint";
#@
#@ set compile_top_all_paths "false"
#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name
#@ #
#@ # These variables affects compile, report_timing and report_constraints
#@ # commands.
#@ #
#@ set enable_recovery_removal_arcs "false"
#@
#@ #
#@ # Multibit Variable Group:
#@ #
#@ # These variables affect the multibit mapping functionality
#@ #
#@
#@ set bus_multiple_separator_style ","
#@
#@ #
#@ # Estimator Variable Group:
#@ #
#@ # These variables affect the designs created by the ESTIMATE command.
#@ #
#@ set estimate_resource_preference "fast"
#@ alias est_resource_preference estimate_resource_preference
#@ set lbo_lfo_enable_at_pin_count 3
#@ set lbo_cells_in_regions "false"
#@
#@ # Synthetic Library Group:
#@ #
#@ # These variable affect synthetic library processing.
#@ #
#@ set cache_dir_chmod_octal "777"
#@ set cache_file_chmod_octal "666"
#@ set cache_read "~"
#@ set cache_read_info "false"
#@ set cache_write "~"
#@ set cache_write_info "false"
#@ set dw_prefer_mc_inside "false"
#@ set mgi_scratch_directory "designware_generator"
#@ set synlib_disable_limited_licenses "true"
#@ set synlib_dont_get_license {}
#@ set synlib_evaluation_mode "false"
#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07 DW08}
#@ set synlib_model_map_effort "medium"
#@ set synlib_optimize_non_cache_elements "true"
#@ set synlib_prefer_ultra_license "false"
#@ set synlib_sequential_module "default"
#@ set synlib_wait_for_design_license {}
#@
#@ #
#@ # Insert_DFT Variable Group:
#@ #
#@ set test_default_client_order [list]
#@ set test_point_keep_hierarchy "false"
#@ set insert_dft_clean_up "true"
#@
#@ #
#@ # Insert_Test Variable Group:
#@ #
#@ # These variables affect the designs created by the INSERT_TEST and INSERT_SCAN commands.
#@ #
#@ set insert_test_design_naming_style "%s_test_%d"
#@ # /*insert_test_scan_chain_only_one_clock = "false"
#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/
#@ set test_clock_port_naming_style "test_c%s"
#@ set test_scan_clock_a_port_naming_style "test_sca%s"
#@ set test_scan_clock_b_port_naming_style "test_scb%s"
#@ set test_scan_clock_port_naming_style "test_sc%s"
#@ set test_scan_enable_inverted_port_naming_style "test_sei%s"
#@ set test_scan_enable_port_naming_style "test_se%s"
#@ set test_scan_in_port_naming_style "test_si%s%s"
#@ set test_scan_out_port_naming_style "test_so%s%s"
#@ set test_non_scan_clock_port_naming_style "test_nsc_%s"
#@ set test_default_min_fault_coverage 95
#@ set insert_test_map_effort_enabled TRUE
#@ set test_dedicated_subdesign_scan_outs "true"
#@ set test_disable_find_best_scan_out "false"
#@ set test_dont_fix_constraint_violations "false"
#@ set test_isolate_hier_scan_out 0
#@ set test_mode_port_naming_style "test_mode%s"
#@ set test_mode_port_inverted_naming_style "test_mode_i%s"
#@ set compile_dont_use_dedicated_scanout 1
#@
#@ #
#@ # Analyze_Scan Variable Group:
#@ #
#@ # These variables affect the designs created by the PREVIEW_SCAN command.
#@ #
#@ set test_preview_scan_shows_cell_types "false"
#@ set test_scan_link_so_lockup_key "l"
#@ set test_scan_link_wire_key "w"
#@ set test_scan_segment_key "s"
#@ set test_scan_true_key "t"
#@ set test_jump_over_bufs_invs "true"
#@
#@ #
#@ # bsd Variable Group:
#@
#@ # These variables affect the report generated by the check_bsd command
#@ # and the BSDLout generated by the write_bsdl command.
#@ #
#@ set test_user_test_data_register_naming_style "UTDR%d"
#@
#@ set test_user_defined_instruction_naming_style "USER%d"
#@
#@ set test_bsdl_default_suffix_name "bsdl"
#@
#@ set test_bsdl_max_line_length 80
#@
#@ set test_cc_ir_masked_bits 0
#@
#@ set test_cc_ir_value_of_masked_bits 0
#@
#@ set test_bsd_allow_tolerable_violations "false"
#@ set test_bsd_optimize_control_cell "false"
#@ set test_bsd_control_cell_drive_limit 0
#@ set test_bsd_manufacturer_id 0
#@ set test_bsd_part_number 0
#@ set test_bsd_version_number 0
#@
#@
#@ #
#@ # TestManager Variable Group:
#@ #
#@ # These variables affect the TestManager methodology.
#@ #
#@ set multi_pass_test_generation "false"
#@
#@ #
#@ # TestSim Variable Group:
#@ #
#@ # These variables affect the TestSim behavior.
#@ #
#@ # set testsim_print_stats_file "true"
#@
#@ # Test DRC Variable Group:
#@ #
#@ # These variables affect the check_test command.
#@ #
#@ set test_capture_clock_skew "small_skew"
#@ set test_allow_clock_reconvergence "true"
#@ set test_check_port_changes_in_capture "true"
#@ set test_infer_slave_clock_pulse_after_capture "infer"
#@
#@ #
#@ # Test Variable Group:
#@ #
#@ # These variables affect the check_test, write_test_protocol
#@ # and write_test command.
#@ #
#@ set test_default_delay 5.0
#@ set test_default_bidir_delay 55.0
#@ set test_default_strobe 95.0
#@ set test_default_strobe_width 0.0
#@ set test_default_period 100.0
#@ set test_default_scan_style "multiplexed_flip_flop"
#@ set test_stil_netlist_format "db"
#@ set test_stil_multiclock_capture_procedures "false"
#@ set test_write_four_cycle_stil_protocol "false"
#@ set test_protocol_add_cycle "true"
#@
#@ #
#@ # JTAG variable group (associated with the insert_jtag command):
#@ #
#@ # These variables are associated with JTAG synthesis.
#@ #
#@ set jtag_port_drive_limit 6
#@ set jtag_manufacturer_id 0
#@ set jtag_version_number 0
#@ set jtag_part_number 65535
#@ set jtag_test_data_in_port_naming_style "jtag_tdi%s"
#@ set jtag_test_data_out_port_naming_style "jtag_tdo%s"
#@ set jtag_test_mode_select_port_naming_style "jtag_tms%s"
#@ set jtag_test_clock_port_naming_style "jtag_tck%s"
#@ set jtag_test_reset_port_naming_style "jtag_trst%s"
#@
#@
#@
#@ #
#@ # Create_Test_Patterns Variable Group:
#@ #
#@ # These variables affect the create_test_patterns command.
#@ #
#@ # From Peace on, the "atpg_test_asynchronous_pins" is obsolete
#@ # set atpg_test_asynchronous_pins "true"
#@
#@ set atpg_bidirect_output_only "false"
#@
#@
#@ #
#@ # Write_Test Variable Group:
#@ #
#@ # These variables affect output of the WRITE_TEST command.
#@ #
#@ set write_test_input_dont_care_value "X"
#@ set write_test_vector_file_naming_style "%s_%d.%s"
#@ set write_test_scan_check_file_naming_style "%s_schk.%s"
#@ set write_test_pattern_set_naming_style "TC_Syn_%d"
#@ set write_test_max_cycles 0
#@ set write_test_max_scan_patterns 0
#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */
#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl}
#@ set write_test_include_scan_cell_info "true"
#@ set write_test_round_timing_values "true"
#@
#@ #
#@ # Schematic and EDIF and Hdl Variable Groups:
#@ #
#@ # These variables affect the schematics created by the
#@ # create_schematic command, define the behavior of the
#@ # DC system EDIF interface, and are for controlling hdl
#@ # reading.
#@ #
#@ set bus_dimension_separator_style {][}
#@ set bus_naming_style {%s[%d]}
#@
#@
#@ #
#@ # Schematic and EDIF Variable Groups:
#@ #
#@ # These variables affect the schematics created by the
#@ # create_schematic command and define the behavior of
#@ # the DC system EDIF interface.
#@ #
#@ set bus_range_separator_style ":"
#@
#@
#@ #
#@ # EDIF and Io Variable Groups:
#@ #
#@ # These variables define the behavior of the DC system EDIF interface and
#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc.
#@
#@ set bus_inference_descending_sort "true"
#@ set bus_inference_style ""
#@ set write_name_nets_same_as_ports "false"
#@ #
#@ # Schematic Variable Group:
#@ #
#@ # These variables affect the schematics created by the
#@ # create_schematic command.
#@ #
#@ set font_library "1_25.font"
#@ set generic_symbol_library "generic.sdb"
#@ set gen_max_ports_on_symbol_side 0
#@ set duplicate_ports "false"
#@ set sheet_sizes {A B C D E infinite mentor_maximum sge_maximum}
#@ set single_group_per_sheet "false"
#@ set use_port_name_for_oscs "true"
#@ set gen_bussing_exact_implicit "false"
#@ set gen_cell_pin_name_separator "/"
#@ set gen_max_compound_name_length 256
#@ set gen_show_created_symbols "false"
#@ set gen_match_ripper_wire_widths "false"
#@ set gen_show_created_busses "false"
#@ set gen_dont_show_single_bit_busses "false"
#@ set gen_single_osc_per_name "false"
#@ set gen_create_netlist_busses "true"
#@ set sort_outputs "false"
#@ set gen_open_name_prefix "Open"
#@ set gen_open_name_postfix ""
#@ set default_schematic_options "-size infinite"
#@ # This setting makes gen use the old way to annotate schematics for
#@ # everything except sheets, which is fast enough.
#@ #
#@ set annotation_control 64
#@
#@ #
#@ # Plot Variable Group:
#@ #
#@ # These variables define the operating system and plotter
#@ # interface to the Design Compiler. These should be set at
#@ # installation time, if needed, and then changed only if you
#@ # start using a new type of plotter.
#@ #
#@ # These four variables must be changed if you use a larger or
#@ # smaller plotter or printer:
#@ #
#@ # plotter_maxx, plotter_maxy, plotter_minx, plotter_miny
#@ #
#@ # See the group of site-specific variables at the top of this
#@ # file to set the name of your printer or plotter.
#@ #
#@ #
#@
#@ set plot_orientation "best_fit"
#@ set plotter_maxx 584
#@ set plotter_maxy 764
#@ set plotter_minx 28
#@ set plotter_miny 28
#@ set plot_scale_factor 100
#@ set plot_box "false"
#@
#@
#@ #
#@ # Io Variable Group:
#@ #
#@ # These variables define the behavior of the DC system
#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc.
#@ #
#@ set db2sge_output_directory ""
#@ set db2sge_scale "2"
#@ set db2sge_overwrite "true"
#@ set db2sge_display_symbol_names "false"
#@
#@
#@ set db2sge_display_pin_names "false"
#@ set db2sge_display_instance_names "false"
#@ set db2sge_use_bustaps "false"
#@ set db2sge_use_compound_names "true"
#@ set db2sge_bit_type "std_logic"
#@ set db2sge_bit_vector_type "std_logic_vector"
#@ set db2sge_one_name "'1'"
#@ set db2sge_zero_name "'0'"
#@ set db2sge_unknown_name "'X'"
#@ set db2sge_target_xp "false"
#@ set db2sge_tcf_package_file "synopsys_tcf.vhd"
#@ set db2sge_use_lib_section ""
#@ set db2sge_script ""
#@ set db2sge_command ""
#@ set equationout_and_sign "*"
#@ set equationout_or_sign "+"
#@ set equationout_postfix_negation "true"
#@ set lsiin_net_name_prefix "NET_"
#@ set lsiout_inverter_cell ""
#@ set lsiout_upcase "true"
#@ set mentor_bidirect_value "INOUT"
#@ set mentor_do_path ""
#@ set mentor_input_output_property_name "PINTYPE"
#@ set mentor_input_value "IN"
#@ set mentor_logic_one_value "1SF"
#@ set mentor_logic_zero_one_property_name "INIT"
#@ set mentor_logic_zero_value "0SF"
#@ set mentor_output_value "OUT"
#@ set mentor_primitive_property_name "PRIMITIVE"
#@ set mentor_primitive_property_value "MODULE"
#@ set mentor_reference_property_name "COMP"
#@ set mentor_search_path ""
#@ set mentor_write_symbols "true"
#@ set pla_read_create_flip_flop "false"
#@ set tdlout_upcase "true"
#@ set xnfout_constraints_per_endpoint "50"
#@ set xnfout_default_time_constraints true
#@ set xnfout_clock_attribute_style "CLK_ONLY"
#@ set xnfout_library_version ""
#@ set xnfin_family "4000"
#@ set xnfin_ignore_pins "GTS GSR GR"
#@ set xnfin_dff_reset_pin_name "RD"
#@ set xnfin_dff_set_pin_name "SD"
#@ set xnfin_dff_clock_enable_pin_name "CE"
#@ set xnfin_dff_data_pin_name "D"
#@ set xnfin_dff_clock_pin_name "C"
#@ set xnfin_dff_q_pin_name "Q"
#@
#@
#@ #
#@ # EDIF Variable Group:
#@ #
#@ # These variables define the behavior of the DC system
#@ # EDIF interface.
#@ #
#@ set bus_extraction_style {%s[%d:%d]}
#@ set edifin_autoconnect_offpageconnectors "false"
#@ set edifin_autoconnect_ports "false"
#@ set edifin_dc_script_flag ""
#@ set edifin_delete_empty_cells "true"
#@ set edifin_delete_ripper_cells "true"
#@ set edifin_ground_net_name ""
#@ set edifin_ground_net_property_name ""
#@ set edifin_ground_net_property_value ""
#@ set edifin_ground_port_name ""
#@ set edifin_instance_property_name ""
#@ set edifin_portinstance_disabled_property_name ""
#@ set edifin_portinstance_disabled_property_value ""
#@ set edifin_portinstance_property_name ""
#@ set edifin_power_net_name ""
#@ set edifin_power_net_property_name ""
#@ set edifin_power_net_property_value ""
#@ set edifin_power_port_name ""
#@ set edifin_use_identifier_in_rename "false"
#@ set edifin_view_identifier_property_name ""
#@ set edifin_lib_logic_1_symbol ""
#@ set edifin_lib_logic_0_symbol ""
#@ set edifin_lib_in_port_symbol ""
#@ set edifin_lib_out_port_symbol ""
#@ set edifin_lib_inout_port_symbol ""
#@ set edifin_lib_in_osc_symbol ""
#@ set edifin_lib_out_osc_symbol ""
#@ set edifin_lib_inout_osc_symbol ""
#@ set edifin_lib_mentor_netcon_symbol ""
#@ set edifin_lib_ripper_bits_property ""
#@ set edifin_lib_ripper_bus_end ""
#@ set edifin_lib_ripper_cell_name ""
#@ set edifin_lib_ripper_view_name ""
#@ set edifin_lib_route_grid 1024
#@ set edifin_lib_templates {}
#@ set edifout_dc_script_flag ""
#@ set edifout_design_name "Synopsys_edif"
#@ set edifout_designs_library_name "DESIGNS"
#@ set edifout_display_instance_names "false"
#@ set edifout_display_net_names "false"
#@ set edifout_external "true"
#@ set edifout_external_graphic_view_name "Graphic_representation"
#@ set edifout_external_netlist_view_name "Netlist_representation"
#@ set edifout_external_schematic_view_name "Schematic_representation"
#@ set edifout_ground_name "logic_0"
#@ set edifout_ground_net_name ""
#@ set edifout_ground_net_property_name ""
#@ set edifout_ground_net_property_value ""
#@ set edifout_ground_pin_name "logic_0_pin"
#@ set edifout_ground_port_name "GND"
#@ set edifout_instance_property_name ""
#@ set edifout_instantiate_ports "false"
#@ set edifout_library_graphic_view_name "Graphic_representation"
#@ set edifout_library_netlist_view_name "Netlist_representation"
#@ set edifout_library_schematic_view_name "Schematic_representation"
#@ set edifout_merge_libraries "false"
#@ set edifout_multidimension_arrays "false"
#@ set edifout_name_oscs_different_from_ports "false"
#@ set edifout_name_rippers_same_as_wires "false"
#@ set edifout_netlist_only "false"
#@ set edifout_no_array "false"
#@ set edifout_numerical_array_members "false"
#@ set edifout_pin_direction_in_value ""
#@ set edifout_pin_direction_inout_value ""
#@ set edifout_pin_direction_out_value ""
#@ set edifout_pin_direction_property_name ""
#@ set edifout_pin_name_property_name ""
#@ set edifout_portinstance_disabled_property_name ""
#@ set edifout_portinstance_disabled_property_value ""
#@ set edifout_portinstance_property_name ""
#@ set edifout_power_and_ground_representation "cell"
#@ set edifout_power_name "logic_1"
#@ set edifout_power_net_name ""
#@ set edifout_power_net_property_name ""
#@ set edifout_power_net_property_value ""
#@ set edifout_power_pin_name "logic_1_pin"
#@ set edifout_power_port_name "VDD"
#@ set edifout_skip_port_implementations "false"
#@ set edifout_target_system ""
#@ set edifout_top_level_symbol "true"
#@ set edifout_translate_origin ""
#@ set edifout_unused_property_value ""
#@ set edifout_write_attributes "false"
#@ set edifout_write_constraints "false"
#@ set edifout_write_properties_list {}
#@ set read_name_mapping_nowarn_libraries {}
#@ set write_name_mapping_nowarn_libraries {}
#@
#@ #
#@ # Hdl and Vhdlio Variable Groups:
#@ #
#@ # These variables are for controlling hdl reading, writing,
#@ # and optimizing.
#@ #
#@ set hdlin_advisor_directory "."
#@ set bus_minus_style "-%d"
#@ set hdlin_write_gtech_design_directory "."
#@ set hdlin_enable_analysis_info "false"
#@ set hdlin_hide_resource_line_numbers FALSE
#@ set hdlin_reg_report_length 60
#@ set hdlin_auto_save_templates FALSE
#@ set hdlin_replace_synthetic FALSE
#@ set hdlin_dont_check_param_width FALSE
#@ set hdlin_latch_always_async_set_reset FALSE
#@ set hdlin_ff_always_sync_set_reset FALSE
#@ set hdlin_ff_always_async_set_reset TRUE
#@ set hdlin_check_no_latch FALSE
#@ set hdlin_report_inferred_modules "true"
#@ set hdlin_reg_report_length 60
#@ set hdlin_translate_off_skip_text false
#@ set hdlin_keep_feedback FALSE
#@ set hdlin_keep_inv_feedback TRUE
#@ set hdlin_infer_mux "default"
#@ set hdlin_merge_nested_conditional_statements false
#@ set hdlin_dont_infer_mux_for_resource_sharing "true"
#@ set hdlin_mux_oversize_ratio 100
#@ set hdlin_mux_size_limit 32
#@ set hdlin_infer_multibit "default_none"
#@ set hdlin_enable_vpp false
#@ set hdlin_preserve_vpp_files false
#@ set hdlin_vpp_temporary_directory ""
#@ set hdlin_dont_turbo_instances_with_generics "true"
#@ set hdlin_vhdl93_concat "true"
#@ set hdlin_enable_rtldrc_info "false"
#@ set hdl_preferred_license ""
#@ set hdl_keep_licenses "true"
#@ set hlo_resource_allocation "constraint_driven"
#@ set hlo_transform_constant_multiplication "false"
#@ set hlo_minimize_tree_delay true
#@ set hlo_resource_implementation "use_fastest"
#@ set hlo_share_common_subexpressions true
#@ set hlo_share_effort low
#@ set hlo_ignore_priorities false
#@ set sdfout_top_instance_name ""
#@ set sdfout_time_scale 1.0
#@ set sdfout_min_rise_net_delay 0.
#@ set sdfout_min_fall_net_delay 0.
#@ set sdfout_min_rise_cell_delay 0.
#@ set sdfout_min_fall_cell_delay 0.
#@ set sdfout_write_to_output "false"
#@ set sdfout_allow_non_positive_constraints "false"
#@ set sdfin_top_instance_name ""
#@ set sdfin_min_rise_net_delay 0.
#@ set sdfin_min_fall_net_delay 0.
#@ set sdfin_min_rise_cell_delay 0.
#@ set sdfin_min_fall_cell_delay 0.
#@ set sdfin_rise_net_delay_type "maximum"
#@ set sdfin_fall_net_delay_type "maximum"
#@ set sdfin_rise_cell_delay_type "maximum"
#@ set sdfin_fall_cell_delay_type "maximum"
#@ set site_info_file ${synopsys_root}/admin/license/site_info
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ alias site_info sh cat $site_info_file
#@ } else {
#@ alias site_info "sh cat site_info_file"
#@ }
#@ set hdl_naming_threshold 20
#@ set template_naming_style "%s_%p"
#@ set template_parameter_style "%s%d"
#@ set template_separator_style "_"
#@ set design_library_file ".synopsys_vss.setup"
#@ set verilogout_equation "false"
#@ set verilogout_ignore_case "false"
#@ set verilogout_no_tri "false"
#@ set verilogout_single_bit "false"
#@ set verilogout_higher_designs_first "FALSE"
#@ set verilogout_levelize "FALSE"
#@ set verilogout_include_files {}
#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_"
#@ set verilogout_show_unconnected_pins "FALSE"
#@ set verilogout_no_negative_index "FALSE"
#@ set vhdlout_architecture_name "SYN_%a_%u"
#@ set vhdlout_bit_type "std_logic"
#@ set vhdlout_bit_type_resolved "TRUE"
#@ set vhdlout_bit_vector_type "std_logic_vector"
#@ set vhdlout_conversion_functions {}
#@ set vhdlout_dont_write_types "FALSE"
#@ set vhdlout_equations "FALSE"
#@ set vhdlout_one_name "'1'"
#@ set vhdlout_package_naming_style "CONV_PACK_%d"
#@ set vhdlout_preserve_hierarchical_types "VECTOR"
#@ set vhdlout_separate_scan_in "FALSE"
#@ set vhdlout_single_bit "USER"
#@ set vhdlout_target_simulator ""
#@ set vhdlout_three_state_name "'Z'"
#@ set vhdlout_three_state_res_func ""
#@ set vhdlout_time_scale 1.0
#@ set vhdlout_top_configuration_arch_name "A"
#@ set vhdlout_top_configuration_entity_name "E"
#@ set vhdlout_top_configuration_name "CFG_TB_E"
#@ set vhdlout_unknown_name "'X'"
#@ set vhdlout_upcase "FALSE"
#@ set vhdlout_use_packages {IEEE.std_logic_1164}
#@ set vhdlout_wired_and_res_func ""
#@ set vhdlout_wired_or_res_func ""
#@ set vhdlout_write_architecture "TRUE"
#@ set vhdlout_write_components "TRUE"
#@ set vhdlout_write_entity "TRUE"
#@ set vhdlout_write_top_configuration "FALSE"
#@ set vhdlout_synthesis_off "TRUE"
#@ set vhdlout_zero_name "'0'"
#@ set vhdlout_levelize "FALSE"
#@ set vhdlout_dont_create_dummy_nets "FALSE"
#@ set vhdlout_follow_vector_direction "FALSE"
#@
#@ # variables pertaining to VHDL library generation
#@ set vhdllib_timing_mesg "true"
#@ set vhdllib_timing_xgen "false"
#@ set vhdllib_timing_checks "true"
#@ set vhdllib_negative_constraint "false"
#@ set vhdllib_glitch_handle "true"
#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle"
#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */
#@ set vhdllib_architecture {UDSM, FTSM, FTGS, VITAL}
#@ set vhdllib_tb_compare 0
#@ set vhdllib_tb_x_eq_dontcare FALSE
#@ set vhdllib_logic_system "ieee-1164"
#@ set vhdllib_logical_name ""
#@
#@ # variables pertaining to technology library processing
#@ set read_db_lib_warnings FALSE
#@ set read_translate_msff TRUE
#@ set libgen_max_differences -1
#@
#@ #
#@ # View Variable Group:
#@ #
#@ # These variables define the behavior of the Design_Analyzer.
#@ # Each user may wish to customize the cursor color, or , , etc. of the
#@ # viewer in his/her own .synopsys file.
#@ #
#@ #
#@ set view_maximum_route_grids 0
#@ set view_dialogs_modal "true"
#@ set view_disable_error_windows "false"
#@ set view_error_window_count 6
#@ set view_log_file ""
#@ set view_busy_during_selection "true"
#@ set view_set_cursor_area 5
#@ set view_cache_images "true"
#@ set view_draw_text_breakpoint 0.01
#@ set view_use_integer_scaling "false"
#@ set view_use_x_routines "true"
#@ set view_disable_output "false"
#@ #set view_arch_types {sparcOS5, hpux10, apollo, decmips, hp700, mips, necmips, rs6000, sgimips, sonymips, sun3, sparc}
#@ set view_icon_path ${init_path}/icons
#@ set view_background "black"
#@ set view_disable_cursor_warping "true"
#@ set view_watcher ${bin_path}/da_watcher_exec
#@ set da_ref_manual "synth/daptr/toc.pdf"
#@ set view_command_win_max_lines 1000
#@ set view_select_separator " - "
#@ set view_select_default_message "Left Button: Select - Middle Button: Add/Modify Select - Right Button: Menu"
#@ set view_on_line_doc_cmd ${synopsys_root}/sold
#@ set view_info_search_cmd ${synopsys_root}/infosearch/scripts/InfoSearch
#@ set view_script_submenu_items {}
#@ set x11_set_cursor_number -1
#@ set x11_set_cursor_foreground ""
#@ set x11_set_cursor_background ""
#@ set view_set_selecting_color ""
#@ set view_use_small_cursor ""
#@ # added for star 12763
#@ set view_tools_menu_items {}
#@ # affect the HDL Text Viewer
#@ set text_unselect_on_button_press "true"
#@ set text_editor_command "xterm -fn 8x13 -e vi %s &"
#@ set test_design_analyzer_uses_insert_scan "true"
#@ #
#@ # If you like emacs, uncomment the next line
#@ # set text_editor_command "emacs -fn 8x13 %s &" ;
#@
#@ # You can delete pairs from this list, but you can't add new ones
#@ # unless you also update the UIL files. So, customers can not add
#@ # dialogs to this list, only Synopsys can do that.
#@ #
#@ set view_independent_dialogs { "test_report", " Test Reports ", "report_print", " Report ", "report_options", " Report Options ", "report_win", " Report Output ", "manual_page", " Manual Page " }
#@
#@ # if color Silicon Graphics workstation
#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} {
#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } {
#@ set x11_set_cursor_foreground "magenta"
#@ set view_use_small_cursor "true"
#@ set view_set_selecting_color "white"
#@ }
#@ }
#@
#@ # if running on an Apollo machine
#@ set found_x11_vendor_string_apollo 0
#@ set found_arch_apollo 0
#@ if { [info exists x11_vendor_string]} {
#@ if { $x11_vendor_string == "Apollo "} {
#@ set found_x11_vendor_string_apollo 1
#@ }
#@ }
#@ if { [info exists arch]} {
#@ if { $arch == "apollo"} {
#@ set found_arch_apollo 1
#@ }
#@ }
#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} {
#@ set enable_page_mode "false"
#@ } else {
#@ set enable_page_mode "true"
#@ }
#@
#@ # don't work around this bug on the Apollo
#@ if { $found_x11_vendor_string_apollo == 1} {
#@ set view_extend_thick_lines "false"
#@ } else {
#@ set view_extend_thick_lines "true"
#@ }
#@
#@ #
#@ # Suffix Variable Group:
#@ #
#@ # Suffixes recognized by the Design Analyzer menu in file choices
#@ #
#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf}
#@ set view_analyze_file_suffix {v vhd vhdl}
#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf}
#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con}
#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips}
#@
#@
#@ #
#@ # links_to_layout Variable Group:
#@ #
#@ # These variables affect the read_timing, write_timing
#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design
#@ # commands.
#@ #
#@ set rtl_load_resistance_factor 0.0
#@ set auto_wire_load_selection "true"
#@ set compile_create_wire_load_table "false"
#@
#@ # power Variable Group:
#@ #
#@ # These variables affect the behavior of power analysis.
#@ #
#@ #
#@
#@ set power_keep_license_after_power_commands "false"
#@ set power_rtl_saif_file "power_rtl.saif"
#@ set power_sdpd_saif_file "power_sdpd.saif"
#@ set power_preserve_rtl_hier_names "false"
#@ set power_do_not_size_icg_cells "false"
#@ set power_hdlc_do_not_split_cg_cells "false"
#@
#@ # BC Variable Group:
#@ #
#@ # These variables affect the BC behavior
#@ #
#@ #
#@
#@ #
#@ # BCView
#@ #
#@ set bc_enable_analysis_info "false"
#@
#@ #
#@ # Scheduling
#@ #
#@ set bc_enable_chaining "true"
#@ set bc_enable_multi_cycle "true"
#@ set bc_enable_speculative_execution "false"
#@
#@
#@ #
#@ # Control Generation
#@ #
#@ set bc_fsm_coding_style "one_hot"
#@
#@ #
#@ # Netlisting
#@ #
#@ #Ki-Seok: removed the following 3 variables: Jan. 1999
#@ #/*
#@ #set bc_no_reset_on_datapath "true"
#@ #set bc_clears_all_registers "false"
#@ #set bc_connect_reset "true"
#@ #*/
#@
#@ #/*
#@ # * Timing (bc_time_design and timing estimates during scheduling)
#@ # */
#@ #/* Removed by Suhrid A. Wadekar Feb. 11, 1999.
#@ # * bc_preserved_functions_map_effort is no longer supported
#@ # */
#@ #/*
#@ #set bc_preserved_functions_map_effort "medium"
#@ #*/
#@ set bc_time_all_sequential_op_bindings "false"
#@ set bc_estimate_mux_input 4
#@ set bc_estimate_timing_effort "high"
#@
#@ #/*
#@ # * Memories
#@ # */
#@ set bc_allow_shared_memories "false"
#@ set bc_constrain_signal_memories "false"
#@ set bc_detect_memory_accesses "false"
#@ set bc_detect_array_accesses "false"
#@ set bc_chain_read_into_mem "true"
#@ set bc_chain_read_into_oper "true"
#@
#@ #/*
#@ # * Logic grouping
#@ # */
#@ set bc_group_eql_logic "true"
#@ set bc_group_index_logic "true"
#@ set bc_use_registerfiles "false"
#@
#@ #
#@ # Reporting
#@ #
#@ set bc_report_filter ""
#@
#@ #
#@ # RTLout debug mode
#@ #
#@ set vhdlout_debug_mode "false"
#@ set verilogout_debug_mode "false"
#@
#@ # Synthesizable RTLOUT variables
#@ set bc_synrtl_map_to_gtech "true"
#@ set bc_synrtl_write_precompiled_designware "false"
#@ set bc_synrtl_write_preserved_functions "false"
#@ set bc_synrtl_write_dcsh_
xcoco (从来就是这样酷...) 于 (Wed Aug 24 16:05:36 2005) 提到:
从网上下了一个电路的verilog逻辑网表，用DC综合了一下，一切正常，可在等价性检查时却报告两个电路的很多输出端都不等价，为什么呢？如果综合出来的电路和原设计功能都不一样，那还作什么啊？问题出在哪里？
等价验证用的是Prover的echeck，是基于形式验证的。
谢谢
☆─────────────────────────────────────☆
QArk (SapphireSequenceDesign) 于 (Wed Aug 24 16:09:20 2005) 提到:
可能有COT吧，把LOG 文件传上来看看
【 在 xcoco (从来就是这样酷...) 的大作中提到: 】
: 从网上下了一个电路的verilog逻辑网表，用DC综合了一下，一切正常，可在等价性检查时却报告两个电路的很多输出端都不等价，为什么呢？如果综合出来的电路和原设计功能都不一样，那还作什么啊？问题出在哪里？
: 等价验证用的是Prover的echeck，是基于形式验证的。
: 谢谢
: ...................
☆─────────────────────────────────────☆
xcoco (从来就是这样酷...) 于 (Wed Aug 24 18:39:09 2005) 提到:
COT？不太明白，你是说我用了自己的库？我用的是dc的10k的库，而且还没做constraint，实在不明白哪里出了问题。下面是dc的log
#@ #
#@ # Running dc_shell Version 2000.05-1 -- Jul 12, 2000
#@ # Date: Wed Aug 24 14:34:55 2005
#@
source e:/Synopsys/admin/setup/.synopsys_dc.setup
#@ #
#@ #
#@ # ".synopsys_dc.setup" Initialization File for
#@ #
#@ # Dc_Shell and Design_Analyzer
#@ #
#@ # The variables in this file define the behavior of many parts
#@ # of the Synopsys Synthesis Tools. Upon installation, they should
#@ # be reviewed and modified to fit your site's needs. Each engineer
#@ # can have a .synopsys file in his/her home directory or current
#@ # directory to override variable settings in this file.
#@ #
#@ # Each logical grouping of variables is commented as to their
#@ # nature and effect on the Synthesis Commands. Examples of
#@ # variable groups are the Compile Variable Group, which affects
#@ # the designs produced by the COMPILE command, and the Schematic
#@ # Variable Group, which affects the output of the create_schematic
#@ # command.
#@ #
#@ # You can type "man <group_name>_variables" in dc_shell or
#@ # design_analyzer to get help about a group of variables.
#@ # For instance, to get help about the "system" variable group,
#@ # type "help system_variables". You can also type
#@ # "man <variable name>", to get help on the that variable's
#@ # group.
#@ #
#@
#@ # System variables
#@ set sh_command_abbrev_mode "Anywhere"
#@ set sh_continue_on_error "true"
#@ set sh_enable_page_mode "true"
#@ set sh_source_uses_search_path "true"
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ set sh_command_log_file "./command.log"
#@ }
#@
#@
#@
#@ # Enable debug output on fatal
#@ if { ( ( ( $sh_arch == {sparc}) || ( $sh_arch == {sparcOS5})) || ( $sh_arch == {hp700})) || ( $sh_arch == {hpux10}) } {
#@ setenv SYNOPSYS_TRACE {}
#@ }
#@
#@ #
#@ # Load the procedures which make up part of the user interface.
#@ #
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ source $synopsys_root/auxx/syn/.dc_common_procs.tcl
#@ source $synopsys_root/auxx/syn/.dc_procs.tcl
#@ alias list_commands help
#@ }
#@ ##############################################################################
#@ #
#@ #
#@ # FILE: auxx/syn/.dc_common_procs.tcl
#@ #
#@ # ABSTRACT: These procedures are part of the PrimeTime and DC
#@ # user interface.
#@ # They are loaded by .synopsys_pt.setup and .synopsys_dc.setup.
#@ #
#@ ##############################################################################
#@ #
#@ #
#@
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: group_variable
#@ #
#@ # ABSTRACT: Add a variable to the specified variable group.
#@ # This command is typically used by the system
#@ # administrator only.
#@ #
#@ # Below the proc is the command which creates the command
#@ # help information and semantic data for the argument.
#@ #
#@ # RETURNS: 1 if it is successful.
#@ # error code if the variable does not exist.
#@ # error code of the variable is already in the group.
#@ #
#@ # SYNTAX: group_variable group_name variable_name
#@ #
#@ ##############################################################################
#@ #
#@
#@
#@ proc group_variable { args } {
#@ global _Variable_Groups
#@
#@ parse_proc_arguments -args $args resarr
#@ set group $resarr(group)
#@ set var $resarr(variable_name)
#@
#@ if { ![info exists _Variable_Groups($group)] } {
#@ set _Variable_Groups($group) ""
#@ }
#@
#@ # Verify that var exists as a global variable
#@
#@ set cmd "uplevel #0 \{info exists $var\}"
#@ if { ![eval $cmd] } {
#@ return -code error "Variable '$var' is not defined."
#@ }
#@
#@ # Only add it if it's not already there
#@
#@ if { [lsearch $_Variable_Groups($group) $var] == -1 } {
#@ lappend _Variable_Groups($group) $var
#@ }
#@
#@ return 1
#@ }
#@
#@ define_proc_attributes group_variable -info "Add a variable to a variable group" -command_group "Builtins" -permanent -dont_abbrev -define_args {
#@ {group "Variable group name" group}
#@ {variable_name "Variable name" variable_name}}
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: print_variable_group
#@ #
#@ # ABSTRACT: Shows variables and their values defined in the given group.
#@
#@ #
#@ # Below the proc is the command which creates the command
#@ # help information and semantic data for the argument.
#@ #
#@ # RETURNS: 1 if it is successful.
#@ # error code of the variable group does not exist.
#@ #
#@ # SYNTAX: print_variable_group group_name
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc print_variable_group { args } {
#@ global _Variable_Groups
#@
#@ parse_proc_arguments -args $args resarr
#@ set group $resarr(group)
#@
#@ if { [string compare $group "all"] == 0 } {
#@ set cmd "uplevel #0 \{printvar\}"
#@ return [eval $cmd]
#@ }
#@
#@ if { ![info exists _Variable_Groups($group)] } {
#@ return -code error "Variable group '$group' does not exist."
#@ }
#@
#@ # Print out each global variable in the list. To be totally bulletproof,
#@ # test that each variable in the group is still defined. If not, remove
#@ # it from the list.
#@
#@ foreach var [lsort $_Variable_Groups($group)] {
#@ set cmd "uplevel #0 \{info exists $var\}"
#@ if { ![eval $cmd] } {
#@ # Remove it
#@ set n [lsearch $_Variable_Groups($group) $var]
#@ set $_Variable_Groups($group) [lreplace $_Variable_Groups($group) $n $n]
#@ } else {
#@ # Print it.
#@ set cmd "uplevel #0 \{set $var\}"
#@ set val [eval $cmd]
#@ echo [format "%-25s = \"%s\"" $var $val]
#@ }
#@ }
#@
#@ return 1
#@ }
#@
#@ define_proc_attributes print_variable_group -info "Print the contents of a variable group" -command_group "Builtins" -permanent -define_args {{group "Variable group name" group}}
#@
#@ # -- End source e:/Synopsys/auxx/syn/.dc_common_procs.tcl
#@ ##############################################################################
#@ #
#@ #
#@ # FILE: auxx/syn/.dc_procs.tcl
#@ #
#@ # ABSTRACT: These procedures are part of the Design Compiler Tcl
#@ # user interface.
#@ # They are loaded by .synopsys_dc.setup.
#@ #
#@ ##############################################################################
#@ #
#@ #
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_verilog
#@ #
#@ # ABSTRACT: Emulate PT's read_verilog command in DC:
#@ #
#@ # Usage: read_verilog # Read one or more verilog files
#@ # *[-hdl_compiler] (Use HDL Compiler (ignored))
#@ # file_names (Files to read)
#@ #
#@ # Modified: Bharat 11/17/99. Use uplevel to ensure that the command
#@ # sees user/hidden variables from the top level. Star 92970.
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc read_verilog { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format verilog [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_verilog -info " Read one or more verilog files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}
#@ {-hdl_compiler "Use HDL Compiler (ignored)" "" boolean {hidden optional}}
#@ }
#@
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_vhdl
#@ #
#@ # ABSTRACT: Emulate PT's read_vhdl command in DC:
#@ #
#@ # Usage: read_vhdl # Read one or more vhdl files
#@ # file_names (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc read_vhdl { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format vhdl [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_vhdl -info " Read one or more vhdl files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}}
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_db
#@ #
#@ # ABSTRACT: Emulate PT's read_db command in DC:
#@ #
#@ # Usage:
#@ # read_db # Read one or more db files
#@ # *[-netlist_only] (Do not read any attributes from db (ignored))
#@ # *[-library] (File is a library DB (ignored))
#@ # file_names (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@
#@ proc read_db { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format db [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_db -info " Read one or more db files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}
#@ {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}}
#@ {-library "File is a library DB (ignored)" "" boolean {hidden optional}}
#@ }
#@
#@ ##############################################################################
#@ #
#@ #
#@ # PROCEDURE: read_edif
#@ #
#@ # ABSTRACT: Emulate PT's read_edif command in DC:
#@ #
#@ # Usage:
#@ # read_edif # Read one or more edif files
#@ # *[-complete_language] (Use ptxr to read the file (ignored))
#@ # file_names (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@ proc read_edif { args } {
#@ parse_proc_arguments -args $args ra
#@
#@ set cmd [format {read_file -format edif [list %s]} $ra(file_names)]
#@ return [uplevel #0 $cmd]
#@ }
#@
#@ define_proc_attributes read_edif -info " Read one or more edif files" -permanent -define_args {
#@ {file_names "Files to read" file_names list required}
#@ {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}}
#@ }
#@
#@ # -- End source e:/Synopsys/auxx/syn/.dc_procs.tcl
#@
#@ # Temporary fix for the LMC_HOME variable- set it to an empty string
#@
#@ if { [catch {getenv LMC_HOME } __err ] != 0 } {
#@ setenv LMC_HOME ""
#@ }
#@
#@
#@ #
#@ #
#@ # Site-Specific Variables
#@ #
#@ # These are the variables that are most commonly changed at a
#@ # specific site, either upon installation of the Synopsys software,
#@ # or by specific engineers in their local .synopsys files.
#@ #
#@ #
#@
#@ # from the System Variable Group
#@ set link_force_case "check_reference"
#@ set link_library { * your_library.db }
#@
#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/dw/sim_ver]
#@ set target_library your_library.db
#@ set synthetic_library ""
#@ set command_log_file "./command.log"
#@ set designer ""
#@ set company ""
#@ set find_converts_name_lists "false"
#@
#@ set symbol_library your_library.sdb
#@
#@ # from the Schematic Variable Group
#@
#@ # from the Plot Variable Group
#@ if { $sh_arch == "hp700" } {
#@ set plot_command "lp -d"
#@ } else {
#@ set plot_command "lpr -Plw"
#@ }
#@
#@ set view_command_log_file "./view_command.log"
#@
#@ # from the View Variable group
#@ if { $sh_arch == "hp700" } {
#@ set text_print_command "lp -d"
#@ } else {
#@ set text_print_command "lpr -Plw"
#@ }
#@ #
#@ # System Variable Group:
#@ #
#@ # These variables are system-wide variables.
#@ #
#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid
#@ set auto_link_disable "false"
#@ set auto_link_options "-all"
#@ set uniquify_naming_style "%s_%d"
#@ set verbose_messages "true"
#@ set echo_include_commands "true"
#@ set preserve_subshells "hdl_shell_exec"
#@ set suppress_errors {PWR-18 OPT-931 OPT-932}
#@ set change_names_update_inst_tree "true"
#@ set change_names_dont_change_bus_members false
#@ set default_name_rules ""
#@
#@ #
#@ # Compile Variable Group:
#@ #
#@ # These variables affect the designs created by the COMPILE command.
#@ #
#@ set compile_assume_fully_decoded_three_state_busses "false"
#@ set compile_automatic_clock_phase_inference "strict"
#@ set compile_no_new_cells_at_top_level "false"
#@ set compile_dont_touch_annotated_cell_during_inplace_opt "false"
#@ set compile_update_annotated_delays_during_inplace_opt "true"
#@ set compile_instance_name_prefix "U"
#@ set compile_instance_name_suffix ""
#@ set compile_negative_logic_methodology "false"
#@ set compile_disable_hierarchical_inverter_opt "false"
#@ set compile_use_fast_delay_mode "true"
#@ set compile_use_low_timing_effort "false"
#@ set compile_new_boolean_structure "false"
#@ set compile_fix_cell_degradation "false"
#@ set compile_preserve_subdesign_interfaces "false"
#@ set compile_sequential_area_recovery "false"
#@ set port_complement_naming_style "%s_BAR"
#@ set compile_implementation_selection "true"
#@ set compile_mux_no_boundary_optimization "false"
#@ set compile_create_mux_op_hierarchy "true"
#@ set compile_delete_unloaded_sequential_cells "true"
#@ set reoptimize_design_changed_list_file_name ""
#@ set compile_checkpoint_filename "./CHECKPOINT.db"
#@ set compile_checkpoint_cpu_interval 0.0
#@ set compile_checkpoint_phases "false"
#@ set compile_checkpoint_pre_delay_filename "./CHECKPOINT_PRE_DELAY.db"
#@ set compile_checkpoint_pre_drc1_filename "./CHECKPOINT_PRE_DRC1.db"
#@ set compile_checkpoint_pre_drc2_filename "./CHECKPOINT_PRE_DRC2.db"
#@ set compile_checkpoint_pre_area_filename "./CHECKPOINT_PRE_AREA.db"
#@ set compile_cpu_limit 0.0
#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint";
#@ set compile_top_all_paths "false"
#@ set default_port_connection_class "universal"
#@ set compile_dw_simple_mode "false"
#@ set compile_simple_mode_block_effort "none"
#@ set compile_hold_reduce_cell_count "false"
#@
#@
#@ set ldd_return_val 0
#@ if { [string compare $dc_shell_mode "default"] == 0 } {
#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh
#@ alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val "
#@
#@ }
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl
#@ alias list_duplicate_designs "source $ldd_script; set dc_shell_status $ldd_return_val "
#@ }
#@
#@
#@ set compile_log_format " %elap_time %area %wns %tns %drc %endpoint";
#@
#@ set compile_top_all_paths "false"
#@ alias compile_inplace_changed_list_file_name reoptimize_design_changed_list_file_name
#@ #
#@ # These variables affects compile, report_timing and report_constraints
#@ # commands.
#@ #
#@ set enable_recovery_removal_arcs "false"
#@
#@ #
#@ # Multibit Variable Group:
#@ #
#@ # These variables affect the multibit mapping functionality
#@ #
#@
#@ set bus_multiple_separator_style ","
#@
#@ #
#@ # Estimator Variable Group:
#@ #
#@ # These variables affect the designs created by the ESTIMATE command.
#@ #
#@ set estimate_resource_preference "fast"
#@ alias est_resource_preference estimate_resource_preference
#@ set lbo_lfo_enable_at_pin_count 3
#@ set lbo_cells_in_regions "false"
#@
#@ # Synthetic Library Group:
#@ #
#@ # These variable affect synthetic library processing.
#@ #
#@ set cache_dir_chmod_octal "777"
#@ set cache_file_chmod_octal "666"
#@ set cache_read "~"
#@ set cache_read_info "false"
#@ set cache_write "~"
#@ set cache_write_info "false"
#@ set dw_prefer_mc_inside "false"
#@ set mgi_scratch_directory "designware_generator"
#@ set synlib_disable_limited_licenses "true"
#@ set synlib_dont_get_license {}
#@ set synlib_evaluation_mode "false"
#@ set synlib_library_list {DW01 DW02 DW03 DW04 DW05 DW06 DW07 DW08}
#@ set synlib_model_map_effort "medium"
#@ set synlib_optimize_non_cache_elements "true"
#@ set synlib_prefer_ultra_license "false"
#@ set synlib_sequential_module "default"
#@ set synlib_wait_for_design_license {}
#@
#@ #
#@ # Insert_DFT Variable Group:
#@ #
#@ set test_default_client_order [list]
#@ set test_point_keep_hierarchy "false"
#@ set insert_dft_clean_up "true"
#@
#@ #
#@ # Insert_Test Variable Group:
#@ #
#@ # These variables affect the designs created by the INSERT_TEST and INSERT_SCAN commands.
#@ #
#@ set insert_test_design_naming_style "%s_test_%d"
#@ # /*insert_test_scan_chain_only_one_clock = "false"
#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/
#@ set test_clock_port_naming_style "test_c%s"
#@ set test_scan_clock_a_port_naming_style "test_sca%s"
#@ set test_scan_clock_b_port_naming_style "test_scb%s"
#@ set test_scan_clock_port_naming_style "test_sc%s"
#@ set test_scan_enable_inverted_port_naming_style "test_sei%s"
#@ set test_scan_enable_port_naming_style "test_se%s"
#@ set test_scan_in_port_naming_style "test_si%s%s"
#@ set test_scan_out_port_naming_style "test_so%s%s"
#@ set test_non_scan_clock_port_naming_style "test_nsc_%s"
#@ set test_default_min_fault_coverage 95
#@ set insert_test_map_effort_enabled TRUE
#@ set test_dedicated_subdesign_scan_outs "true"
#@ set test_disable_find_best_scan_out "false"
#@ set test_dont_fix_constraint_violations "false"
#@ set test_isolate_hier_scan_out 0
#@ set test_mode_port_naming_style "test_mode%s"
#@ set test_mode_port_inverted_naming_style "test_mode_i%s"
#@ set compile_dont_use_dedicated_scanout 1
#@
#@ #
#@ # Analyze_Scan Variable Group:
#@ #
#@ # These variables affect the designs created by the PREVIEW_SCAN command.
#@ #
#@ set test_preview_scan_shows_cell_types "false"
#@ set test_scan_link_so_lockup_key "l"
#@ set test_scan_link_wire_key "w"
#@ set test_scan_segment_key "s"
#@ set test_scan_true_key "t"
#@ set test_jump_over_bufs_invs "true"
#@
#@ #
#@ # bsd Variable Group:
#@
#@ # These variables affect the report generated by the check_bsd command
#@ # and the BSDLout generated by the write_bsdl command.
#@ #
#@ set test_user_test_data_register_naming_style "UTDR%d"
#@
#@ set test_user_defined_instruction_naming_style "USER%d"
#@
#@ set test_bsdl_default_suffix_name "bsdl"
#@
#@ set test_bsdl_max_line_length 80
#@
#@ set test_cc_ir_masked_bits 0
#@
#@ set test_cc_ir_value_of_masked_bits 0
#@
#@ set test_bsd_allow_tolerable_violations "false"
#@ set test_bsd_optimize_control_cell "false"
#@ set test_bsd_control_cell_drive_limit 0
#@ set test_bsd_manufacturer_id 0
#@ set test_bsd_part_number 0
#@ set test_bsd_version_number 0
#@
#@
#@ #
#@ # TestManager Variable Group:
#@ #
#@ # These variables affect the TestManager methodology.
#@ #
#@ set multi_pass_test_generation "false"
#@
#@ #
#@ # TestSim Variable Group:
#@ #
#@ # These variables affect the TestSim behavior.
#@ #
#@ # set testsim_print_stats_file "true"
#@
#@ # Test DRC Variable Group:
#@ #
#@ # These variables affect the check_test command.
#@ #
#@ set test_capture_clock_skew "small_skew"
#@ set test_allow_clock_reconvergence "true"
#@ set test_check_port_changes_in_capture "true"
#@ set test_infer_slave_clock_pulse_after_capture "infer"
#@
#@ #
#@ # Test Variable Group:
#@ #
#@ # These variables affect the check_test, write_test_protocol
#@ # and write_test command.
#@ #
#@ set test_default_delay 5.0
#@ set test_default_bidir_delay 55.0
#@ set test_default_strobe 95.0
#@ set test_default_strobe_width 0.0
#@ set test_default_period 100.0
#@ set test_default_scan_style "multiplexed_flip_flop"
#@ set test_stil_netlist_format "db"
#@ set test_stil_multiclock_capture_procedures "false"
#@ set test_write_four_cycle_stil_protocol "false"
#@ set test_protocol_add_cycle "true"
#@
#@ #
#@ # JTAG variable group (associated with the insert_jtag command):
#@ #
#@ # These variables are associated with JTAG synthesis.
#@ #
#@ set jtag_port_drive_limit 6
#@ set jtag_manufacturer_id 0
#@ set jtag_version_number 0
#@ set jtag_part_number 65535
#@ set jtag_test_data_in_port_naming_style "jtag_tdi%s"
#@ set jtag_test_data_out_port_naming_style "jtag_tdo%s"
#@ set jtag_test_mode_select_port_naming_style "jtag_tms%s"
#@ set jtag_test_clock_port_naming_style "jtag_tck%s"
#@ set jtag_test_reset_port_naming_style "jtag_trst%s"
#@
#@
#@
#@ #
#@ # Create_Test_Patterns Variable Group:
#@ #
#@ # These variables affect the create_test_patterns command.
#@ #
#@ # From Peace on, the "atpg_test_asynchronous_pins" is obsolete
#@ # set atpg_test_asynchronous_pins "true"
#@
#@ set atpg_bidirect_output_only "false"
#@
#@
#@ #
#@ # Write_Test Variable Group:
#@ #
#@ # These variables affect output of the WRITE_TEST command.
#@ #
#@ set write_test_input_dont_care_value "X"
#@ set write_test_vector_file_naming_style "%s_%d.%s"
#@ set write_test_scan_check_file_naming_style "%s_schk.%s"
#@ set write_test_pattern_set_naming_style "TC_Syn_%d"
#@ set write_test_max_cycles 0
#@ set write_test_max_scan_patterns 0
#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */
#@ set write_test_formats {synopsys tssi_ascii tds verilog vhdl wgl}
#@ set write_test_include_scan_cell_info "true"
#@ set write_test_round_timing_values "true"
#@
#@ #
#@ # Schematic and EDIF and Hdl Variable Groups:
#@ #
#@ # These variables affect the schematics created by the
#@ # create_schematic command, define the behavior of the
#@ # DC system EDIF interface, and are for controlling hdl
#@ # reading.
#@ #
#@ set bus_dimension_separator_style {][}
#@ set bus_naming_style {%s[%d]}
#@
#@
#@ #
#@ # Schematic and EDIF Variable Groups:
#@ #
#@ # These variables affect the schematics created by the
#@ # create_schematic command and define the behavior of
#@ # the DC system EDIF interface.
#@ #
#@ set bus_range_separator_style ":"
#@
#@
#@ #
#@ # EDIF and Io Variable Groups:
#@ #
#@ # These variables define the behavior of the DC system EDIF interface and
#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc.
#@
#@ set bus_inference_descending_sort "true"
#@ set bus_inference_style ""
#@ set write_name_nets_same_as_ports "false"
#@ #
#@ # Schematic Variable Group:
#@ #
#@ # These variables affect the schematics created by the
#@ # create_schematic command.
#@ #
#@ set font_library "1_25.font"
#@ set generic_symbol_library "generic.sdb"
#@ set gen_max_ports_on_symbol_side 0
#@ set duplicate_ports "false"
#@ set sheet_sizes {A B C D E infinite mentor_maximum sge_maximum}
#@ set single_group_per_sheet "false"
#@ set use_port_name_for_oscs "true"
#@ set gen_bussing_exact_implicit "false"
#@ set gen_cell_pin_name_separator "/"
#@ set gen_max_compound_name_length 256
#@ set gen_show_created_symbols "false"
#@ set gen_match_ripper_wire_widths "false"
#@ set gen_show_created_busses "false"
#@ set gen_dont_show_single_bit_busses "false"
#@ set gen_single_osc_per_name "false"
#@ set gen_create_netlist_busses "true"
#@ set sort_outputs "false"
#@ set gen_open_name_prefix "Open"
#@ set gen_open_name_postfix ""
#@ set default_schematic_options "-size infinite"
#@ # This setting makes gen use the old way to annotate schematics for
#@ # everything except sheets, which is fast enough.
#@ #
#@ set annotation_control 64
#@
#@ #
#@ # Plot Variable Group:
#@ #
#@ # These variables define the operating system and plotter
#@ # interface to the Design Compiler. These should be set at
#@ # installation time, if needed, and then changed only if you
#@ # start using a new type of plotter.
#@ #
#@ # These four variables must be changed if you use a larger or
#@ # smaller plotter or printer:
#@ #
#@ # plotter_maxx, plotter_maxy, plotter_minx, plotter_miny
#@ #
#@ # See the group of site-specific variables at the top of this
#@ # file to set the name of your printer or plotter.
#@ #
#@ #
#@
#@ set plot_orientation "best_fit"
#@ set plotter_maxx 584
#@ set plotter_maxy 764
#@ set plotter_minx 28
#@ set plotter_miny 28
#@ set plot_scale_factor 100
#@ set plot_box "false"
#@
#@
#@ #
#@ # Io Variable Group:
#@ #
#@ # These variables define the behavior of the DC system
#@ # interfaces, i.e. LSI, Mentor, TDL, SGE, etc.
#@ #
#@ set db2sge_output_directory ""
#@ set db2sge_scale "2"
#@ set db2sge_overwrite "true"
#@ set db2sge_display_symbol_names "false"
#@
#@
#@ set db2sge_display_pin_names "false"
#@ set db2sge_display_instance_names "false"
#@ set db2sge_use_bustaps "false"
#@ set db2sge_use_compound_names "true"
#@ set db2sge_bit_type "std_logic"
#@ set db2sge_bit_vector_type "std_logic_vector"
#@ set db2sge_one_name "'1'"
#@ set db2sge_zero_name "'0'"
#@ set db2sge_unknown_name "'X'"
#@ set db2sge_target_xp "false"
#@ set db2sge_tcf_package_file "synopsys_tcf.vhd"
#@ set db2sge_use_lib_section ""
#@ set db2sge_script ""
#@ set db2sge_command ""
#@ set equationout_and_sign "*"
#@ set equationout_or_sign "+"
#@ set equationout_postfix_negation "true"
#@ set lsiin_net_name_prefix "NET_"
#@ set lsiout_inverter_cell ""
#@ set lsiout_upcase "true"
#@ set mentor_bidirect_value "INOUT"
#@ set mentor_do_path ""
#@ set mentor_input_output_property_name "PINTYPE"
#@ set mentor_input_value "IN"
#@ set mentor_logic_one_value "1SF"
#@ set mentor_logic_zero_one_property_name "INIT"
#@ set mentor_logic_zero_value "0SF"
#@ set mentor_output_value "OUT"
#@ set mentor_primitive_property_name "PRIMITIVE"
#@ set mentor_primitive_property_value "MODULE"
#@ set mentor_reference_property_name "COMP"
#@ set mentor_search_path ""
#@ set mentor_write_symbols "true"
#@ set pla_read_create_flip_flop "false"
#@ set tdlout_upcase "true"
#@ set xnfout_constraints_per_endpoint "50"
#@ set xnfout_default_time_constraints true
#@ set xnfout_clock_attribute_style "CLK_ONLY"
#@ set xnfout_library_version ""
#@ set xnfin_family "4000"
#@ set xnfin_ignore_pins "GTS GSR GR"
#@ set xnfin_dff_reset_pin_name "RD"
#@ set xnfin_dff_set_pin_name "SD"
#@ set xnfin_dff_clock_enable_pin_name "CE"
#@ set xnfin_dff_data_pin_name "D"
#@ set xnfin_dff_clock_pin_name "C"
#@ set xnfin_dff_q_pin_name "Q"
#@
#@
#@ #
#@ # EDIF Variable Group:
#@ #
#@ # These variables define the behavior of the DC system
#@ # EDIF interface.
#@ #
#@ set bus_extraction_style {%s[%d:%d]}
#@ set edifin_autoconnect_offpageconnectors "false"
#@ set edifin_autoconnect_ports "false"
#@ set edifin_dc_script_flag ""
#@ set edifin_delete_empty_cells "true"
#@ set edifin_delete_ripper_cells "true"
#@ set edifin_ground_net_name ""
#@ set edifin_ground_net_property_name ""
#@ set edifin_ground_net_property_value ""
#@ set edifin_ground_port_name ""
#@ set edifin_instance_property_name ""
#@ set edifin_portinstance_disabled_property_name ""
#@ set edifin_portinstance_disabled_property_value ""
#@ set edifin_portinstance_property_name ""
#@ set edifin_power_net_name ""
#@ set edifin_power_net_property_name ""
#@ set edifin_power_net_property_value ""
#@ set edifin_power_port_name ""
#@ set edifin_use_identifier_in_rename "false"
#@ set edifin_view_identifier_property_name ""
#@ set edifin_lib_logic_1_symbol ""
#@ set edifin_lib_logic_0_symbol ""
#@ set edifin_lib_in_port_symbol ""
#@ set edifin_lib_out_port_symbol ""
#@ set edifin_lib_inout_port_symbol ""
#@ set edifin_lib_in_osc_symbol ""
#@ set edifin_lib_out_osc_symbol ""
#@ set edifin_lib_inout_osc_symbol ""
#@ set edifin_lib_mentor_netcon_symbol ""
#@ set edifin_lib_ripper_bits_property ""
#@ set edifin_lib_ripper_bus_end ""
#@ set edifin_lib_ripper_cell_name ""
#@ set edifin_lib_ripper_view_name ""
#@ set edifin_lib_route_grid 1024
#@ set edifin_lib_templates {}
#@ set edifout_dc_script_flag ""
#@ set edifout_design_name "Synopsys_edif"
#@ set edifout_designs_library_name "DESIGNS"
#@ set edifout_display_instance_names "false"
#@ set edifout_display_net_names "false"
#@ set edifout_external "true"
#@ set edifout_external_graphic_view_name "Graphic_representation"
#@ set edifout_external_netlist_view_name "Netlist_representation"
#@ set edifout_external_schematic_view_name "Schematic_representation"
#@ set edifout_ground_name "logic_0"
#@ set edifout_ground_net_name ""
#@ set edifout_ground_net_property_name ""
#@ set edifout_ground_net_property_value ""
#@ set edifout_ground_pin_name "logic_0_pin"
#@ set edifout_ground_port_name "GND"
#@ set edifout_instance_property_name ""
#@ set edifout_instantiate_ports "false"
#@ set edifout_library_graphic_view_name "Graphic_representation"
#@ set edifout_library_netlist_view_name "Netlist_representation"
#@ set edifout_library_schematic_view_name "Schematic_representation"
#@ set edifout_merge_libraries "false"
#@ set edifout_multidimension_arrays "false"
#@ set edifout_name_oscs_different_from_ports "false"
#@ set edifout_name_rippers_same_as_wires "false"
#@ set edifout_netlist_only "false"
#@ set edifout_no_array "false"
#@ set edifout_numerical_array_members "false"
#@ set edifout_pin_direction_in_value ""
#@ set edifout_pin_direction_inout_value ""
#@ set edifout_pin_direction_out_value ""
#@ set edifout_pin_direction_property_name ""
#@ set edifout_pin_name_property_name ""
#@ set edifout_portinstance_disabled_property_name ""
#@ set edifout_portinstance_disabled_property_value ""
#@ set edifout_portinstance_property_name ""
#@ set edifout_power_and_ground_representation "cell"
#@ set edifout_power_name "logic_1"
#@ set edifout_power_net_name ""
#@ set edifout_power_net_property_name ""
#@ set edifout_power_net_property_value ""
#@ set edifout_power_pin_name "logic_1_pin"
#@ set edifout_power_port_name "VDD"
#@ set edifout_skip_port_implementations "false"
#@ set edifout_target_system ""
#@ set edifout_top_level_symbol "true"
#@ set edifout_translate_origin ""
#@ set edifout_unused_property_value ""
#@ set edifout_write_attributes "false"
#@ set edifout_write_constraints "false"
#@ set edifout_write_properties_list {}
#@ set read_name_mapping_nowarn_libraries {}
#@ set write_name_mapping_nowarn_libraries {}
#@
#@ #
#@ # Hdl and Vhdlio Variable Groups:
#@ #
#@ # These variables are for controlling hdl reading, writing,
#@ # and optimizing.
#@ #
#@ set hdlin_advisor_directory "."
#@ set bus_minus_style "-%d"
#@ set hdlin_write_gtech_design_directory "."
#@ set hdlin_enable_analysis_info "false"
#@ set hdlin_hide_resource_line_numbers FALSE
#@ set hdlin_reg_report_length 60
#@ set hdlin_auto_save_templates FALSE
#@ set hdlin_replace_synthetic FALSE
#@ set hdlin_dont_check_param_width FALSE
#@ set hdlin_latch_always_async_set_reset FALSE
#@ set hdlin_ff_always_sync_set_reset FALSE
#@ set hdlin_ff_always_async_set_reset TRUE
#@ set hdlin_check_no_latch FALSE
#@ set hdlin_report_inferred_modules "true"
#@ set hdlin_reg_report_length 60
#@ set hdlin_translate_off_skip_text false
#@ set hdlin_keep_feedback FALSE
#@ set hdlin_keep_inv_feedback TRUE
#@ set hdlin_infer_mux "default"
#@ set hdlin_merge_nested_conditional_statements false
#@ set hdlin_dont_infer_mux_for_resource_sharing "true"
#@ set hdlin_mux_oversize_ratio 100
#@ set hdlin_mux_size_limit 32
#@ set hdlin_infer_multibit "default_none"
#@ set hdlin_enable_vpp false
#@ set hdlin_preserve_vpp_files false
#@ set hdlin_vpp_temporary_directory ""
#@ set hdlin_dont_turbo_instances_with_generics "true"
#@ set hdlin_vhdl93_concat "true"
#@ set hdlin_enable_rtldrc_info "false"
#@ set hdl_preferred_license ""
#@ set hdl_keep_licenses "true"
#@ set hlo_resource_allocation "constraint_driven"
#@ set hlo_transform_constant_multiplication "false"
#@ set hlo_minimize_tree_delay true
#@ set hlo_resource_implementation "use_fastest"
#@ set hlo_share_common_subexpressions true
#@ set hlo_share_effort low
#@ set hlo_ignore_priorities false
#@ set sdfout_top_instance_name ""
#@ set sdfout_time_scale 1.0
#@ set sdfout_min_rise_net_delay 0.
#@ set sdfout_min_fall_net_delay 0.
#@ set sdfout_min_rise_cell_delay 0.
#@ set sdfout_min_fall_cell_delay 0.
#@ set sdfout_write_to_output "false"
#@ set sdfout_allow_non_positive_constraints "false"
#@ set sdfin_top_instance_name ""
#@ set sdfin_min_rise_net_delay 0.
#@ set sdfin_min_fall_net_delay 0.
#@ set sdfin_min_rise_cell_delay 0.
#@ set sdfin_min_fall_cell_delay 0.
#@ set sdfin_rise_net_delay_type "maximum"
#@ set sdfin_fall_net_delay_type "maximum"
#@ set sdfin_rise_cell_delay_type "maximum"
#@ set sdfin_fall_cell_delay_type "maximum"
#@ set site_info_file ${synopsys_root}/admin/license/site_info
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@ alias site_info sh cat $site_info_file
#@ } else {
#@ alias site_info "sh cat site_info_file"
#@ }
#@ set hdl_naming_threshold 20
#@ set template_naming_style "%s_%p"
#@ set template_parameter_style "%s%d"
#@ set template_separator_style "_"
#@ set design_library_file ".synopsys_vss.setup"
#@ set verilogout_equation "false"
#@ set verilogout_ignore_case "false"
#@ set verilogout_no_tri "false"
#@ set verilogout_single_bit "false"
#@ set verilogout_higher_designs_first "FALSE"
#@ set verilogout_levelize "FALSE"
#@ set verilogout_include_files {}
#@ set verilogout_unconnected_prefix "SYNOPSYS_UNCONNECTED_"
#@ set verilogout_show_unconnected_pins "FALSE"
#@ set verilogout_no_negative_index "FALSE"
#@ set vhdlout_architecture_name "SYN_%a_%u"
#@ set vhdlout_bit_type "std_logic"
#@ set vhdlout_bit_type_resolved "TRUE"
#@ set vhdlout_bit_vector_type "std_logic_vector"
#@ set vhdlout_conversion_functions {}
#@ set vhdlout_dont_write_types "FALSE"
#@ set vhdlout_equations "FALSE"
#@ set vhdlout_one_name "'1'"
#@ set vhdlout_package_naming_style "CONV_PACK_%d"
#@ set vhdlout_preserve_hierarchical_types "VECTOR"
#@ set vhdlout_separate_scan_in "FALSE"
#@ set vhdlout_single_bit "USER"
#@ set vhdlout_target_simulator ""
#@ set vhdlout_three_state_name "'Z'"
#@ set vhdlout_three_state_res_func ""
#@ set vhdlout_time_scale 1.0
#@ set vhdlout_top_configuration_arch_name "A"
#@ set vhdlout_top_configuration_entity_name "E"
#@ set vhdlout_top_configuration_name "CFG_TB_E"
#@ set vhdlout_unknown_name "'X'"
#@ set vhdlout_upcase "FALSE"
#@ set vhdlout_use_packages {IEEE.std_logic_1164}
#@ set vhdlout_wired_and_res_func ""
#@ set vhdlout_wired_or_res_func ""
#@ set vhdlout_write_architecture "TRUE"
#@ set vhdlout_write_components "TRUE"
#@ set vhdlout_write_entity "TRUE"
#@ set vhdlout_write_top_configuration "FALSE"
#@ set vhdlout_synthesis_off "TRUE"
#@ set vhdlout_zero_name "'0'"
#@ set vhdlout_levelize "FALSE"
#@ set vhdlout_dont_create_dummy_nets "FALSE"
#@ set vhdlout_follow_vector_direction "FALSE"
#@
#@ # variables pertaining to VHDL library generation
#@ set vhdllib_timing_mesg "true"
#@ set vhdllib_timing_xgen "false"
#@ set vhdllib_timing_checks "true"
#@ set vhdllib_negative_constraint "false"
#@ set vhdllib_glitch_handle "true"
#@ set vhdllib_pulse_handle "use_vhdllib_glitch_handle"
#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */
#@ set vhdllib_architecture {UDSM, FTSM, FTGS, VITAL}
#@ set vhdllib_tb_compare 0
#@ set vhdllib_tb_x_eq_dontcare FALSE
#@ set vhdllib_logic_system "ieee-1164"
#@ set vhdllib_logical_name ""
#@
#@ # variables pertaining to technology library processing
#@ set read_db_lib_warnings FALSE
#@ set read_translate_msff TRUE
#@ set libgen_max_differences -1
#@
#@ #
#@ # View Variable Group:
#@ #
#@ # These variables define the behavior of the Design_Analyzer.
#@ # Each user may wish to customize the cursor color, or , , etc. of the
#@ # viewer in his/her own .synopsys file.
#@ #
#@ #
#@ set view_maximum_route_grids 0
#@ set view_dialogs_modal "true"
#@ set view_disable_error_windows "false"
#@ set view_error_window_count 6
#@ set view_log_file ""
#@ set view_busy_during_selection "true"
#@ set view_set_cursor_area 5
#@ set view_cache_images "true"
#@ set view_draw_text_breakpoint 0.01
#@ set view_use_integer_scaling "false"
#@ set view_use_x_routines "true"
#@ set view_disable_output "false"
#@ #set view_arch_types {sparcOS5, hpux10, apollo, decmips, hp700, mips, necmips, rs6000, sgimips, sonymips, sun3, sparc}
#@ set view_icon_path ${init_path}/icons
#@ set view_background "black"
#@ set view_disable_cursor_warping "true"
#@ set view_watcher ${bin_path}/da_watcher_exec
#@ set da_ref_manual "synth/daptr/toc.pdf"
#@ set view_command_win_max_lines 1000
#@ set view_select_separator " - "
#@ set view_select_default_message "Left Button: Select - Middle Button: Add/Modify Select - Right Button: Menu"
#@ set view_on_line_doc_cmd ${synopsys_root}/sold
#@ set view_info_search_cmd ${synopsys_root}/infosearch/scripts/InfoSearch
#@ set view_script_submenu_items {}
#@ set x11_set_cursor_number -1
#@ set x11_set_cursor_foreground ""
#@ set x11_set_cursor_background ""
#@ set view_set_selecting_color ""
#@ set view_use_small_cursor ""
#@ # added for star 12763
#@ set view_tools_menu_items {}
#@ # affect the HDL Text Viewer
#@ set text_unselect_on_button_press "true"
#@ set text_editor_command "xterm -fn 8x13 -e vi %s &"
#@ set test_design_analyzer_uses_insert_scan "true"
#@ #
#@ # If you like emacs, uncomment the next line
#@ # set text_editor_command "emacs -fn 8x13 %s &" ;
#@
#@ # You can delete pairs from this list, but you can't add new ones
#@ # unless you also update the UIL files. So, customers can not add
#@ # dialogs to this list, only Synopsys can do that.
#@ #
#@ set view_independent_dialogs { "test_report", " Test Reports ", "report_print", " Report ", "report_options", " Report Options ", "report_win", " Report Output ", "manual_page", " Manual Page " }
#@
#@ # if color Silicon Graphics workstation
#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} {
#@ if { $x11_vendor_string == "Silicon" && $x11_is_color == "true" } {
#@ set x11_set_cursor_foreground "magenta"
#@ set view_use_small_cursor "true"
#@ set view_set_selecting_color "white"
#@ }
#@ }
#@
#@ # if running on an Apollo machine
#@ set found_x11_vendor_string_apollo 0
#@ set found_arch_apollo 0
#@ if { [info exists x11_vendor_string]} {
#@ if { $x11_vendor_string == "Apollo "} {
#@ set found_x11_vendor_string_apollo 1
#@ }
#@ }
#@ if { [info exists arch]} {
#@ if { $arch == "apollo"} {
#@ set found_arch_apollo 1
#@ }
#@ }
#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} {
#@ set enable_page_mode "false"
#@ } else {
#@ set enable_page_mode "true"
#@ }
#@
#@ # don't work around this bug on the Apollo
#@ if { $found_x11_vendor_string_apollo == 1} {
#@ set view_extend_thick_lines "false"
#@ } else {
#@ set view_extend_thick_lines "true"
#@ }
#@
#@ #
#@ # Suffix Variable Group:
#@ #
#@ # Suffixes recognized by the Design Analyzer menu in file choices
#@ #
#@ set view_read_file_suffix {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf}
#@ set view_analyze_file_suffix {v vhd vhdl}
#@ set view_write_file_suffix {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf}
#@ set view_execute_script_suffix {.script .scr .dcs .dcv .dc .con}
#@ set view_arch_types {sparcOS5 hpux10 rs6000 sgimips}
#@
#@
#@ #
#@ # links_to_layout Variable Group:
#@ #
#@ # These variables affect the read_timing, write_timing
#@ # set_annotated_delay, compile, create_wire_load and reoptimize_design
#@ # commands.
#@ #
#@ set rtl_load_resistance_factor 0.0
#@ set auto_wire_load_selection "true"
#@ set compile_create_wire_load_table "false"
#@
#@ # power Variable Group:
#@ #
#@ # These variables affect the behavior of power analysis.
#@ #
#@ #
#@
#@ set power_keep_license_after_power_commands "false"
#@ set power_rtl_saif_file "power_rtl.saif"
#@ set power_sdpd_saif_file "power_sdpd.saif"
#@ set power_preserve_rtl_hier_names "false"
#@ set power_do_not_size_icg_cells "false"
#@ set power_hdlc_do_not_split_cg_cells "false"
#@
#@ # BC Variable Group:
#@ #
#@ # These variables affect the BC behavior
#@ #
#@ #
#@
#@ #
#@ # BCView
#@ #
#@ set bc_enable_analysis_info "false"
#@
#@ #
#@ # Scheduling
#@ #
#@ set bc_enable_chaining "true"
#@ set bc_enable_multi_cycle "true"
#@ set bc_enable_speculative_execution "false"
#@
#@
#@ #
#@ # Control Generation
#@ #
#@ set bc_fsm_coding_style "one_hot"
#@
#@ #
#@ # Netlisting
#@ #
#@ #Ki-Seok: removed the following 3 variables: Jan. 1999
#@ #/*
#@ #set bc_no_reset_on_datapath "true"
#@ #set bc_clears_all_registers "false"
#@ #set bc_connect_reset "true"
#@ #*/
#@
#@ #/*
#@ # * Timing (bc_time_design and timing estimates during scheduling)
#@ # */
#@ #/* Removed by Suhrid A. Wadekar Feb. 11, 1999.
#@ # * bc_preserved_functions_map_effort is no longer supported
#@ # */
#@ #/*
#@ #set bc_preserved_functions_map_effort "medium"
#@ #*/
#@ set bc_time_all_sequential_op_bindings "false"
#@ set bc_estimate_mux_input 4
#@ set bc_estimate_timing_effort "high"
#@
#@ #/*
#@ # * Memories
#@ # */
#@ set bc_allow_shared_memories "false"
#@ set bc_constrain_signal_memories "false"
#@ set bc_detect_memory_accesses "false"
#@ set bc_detect_array_accesses "false"
#@ set bc_chain_read_into_mem "true"
#@ set bc_chain_read_into_oper "true"
#@
#@ #/*
#@ # * Logic grouping
#@ # */
#@ set bc_group_eql_logic "true"
#@ set bc_group_index_logic "true"
#@ set bc_use_registerfiles "false"
#@
#@ #
#@ # Reporting
#@ #
#@ set bc_report_filter ""
#@
#@ #
#@ # RTLout debug mode
#@ #
#@ set vhdlout_debug_mode "false"
#@ set verilogout_debug_mode "false"
#@
#@ # Synthesizable RTLOUT variables
#@ set bc_synrtl_map_to_gtech "true"
#@ set bc_synrtl_write_precompiled_designware "false"
#@ set bc_synrtl_write_preserved_functions "false"
#@ set bc_synrtl_write_dcsh_