问DC约束的问题

如图所示的设计，组合电路是顶层设计的一个子模块，现在要约束组合电路的最大延时，用set_max_delay，但是由于组合电路的输入是由宏单元提供的，驱动单元不好加（如set_driving_cell之类只能用于port），这种情况应该如何处理？
谢谢

In the top level, what is connected to the sub comb module? is it floating?
If it's connected to the macro, the driver model of the macro will be used
automatically. If it's floating, then the driving strength can't be modeled...

谢谢你的回复，还有一些不是很明白
（不好意思，我英文比较差，只能用中文回答了）

So currently the macro is just a black box, right? then you can place the driving cell in the black box.
The driver model is to model the driving ability of one cell, together with the receiver model the delay numbers are calced.