Power FET biasing issue as Vg drops

Before applying the VD of power FET i bias its vg according to datasheet but when i power up the FET by applying its VD its vg drops and FET take less current without any RF signal at input. pls can anybody explain why vg drops ?

Vg drop...What do you mean , Vg goes to 0 V or goes to -2, -3 or less?

If the Vg rise to a large, negative value, the FET may self oscillate.

In any case, if the Vg change it's value, it means that Ig (Gate current) is flowing, once again it's indicative of self oscillation.

To roughly check the FET , you may use a simple handheld DMM , check RDS, and RSD (swap the DMM leads) , then check RGS and RSG ( one open , the other show junction voltage even if DMM is in Ω).

good luck

vg goes to -1.2v from -0.6v and there are some ouput oscillation like comb oscilator how to correct this problem?

Rds is 0.3ohms and Rgs is in Mohms.

well, FET appear NOT broken, at least in DC
If when you are looking into spectrum analizer you see a comb it means the self oscillation is so strong to generate all odd&even harmonics.
The fundamental frequency is the 1st strong line.
Basically there are almost two method to stop self oscillations:

1) Theoretical
Consider the risk during the design. K>1, B1>0, stabilizer resistor, non radiating PCB, cavity smaller than λc. etc. etc.

2) Sperimental
Once the circuit has been produced, try sperimentally to stop oscillation by placing some small piece of absorber like Eccosorb? on RF section . Also, for the DC bias, you may add ferrite in series and shunt capacitors. Capacitors self resonance should be twice or more the oscillation freq.
There are lots of type of absorber, almost all have similar aspect and colour but are very different. The most sold is Emerson&Cuming CR117.

Power Supply roles
Also the power supply may play a role.
Try to add large capacitor (i.e.) 1-10μF around the chassis and connected beteween V+ and GND.
Try to twist the V+ and GND wires and leave V- wire alone

Odd mode oscillation roles:
IF your PowerFET is made by an array of parallel FET, a resistor should be placed between the gates (from gate to gate). Look for "odd mode self oscillations".