what type of biasing configuration is this transistor using?

What type of biasing configuration is this transistor using, and how would you explain the setup with the resistors? the image is shown below. Could this be using dual feedback configuration or voltage divider configuration, or something else?

Common Source with Source Degeneration.( For Lowest Noise Matching )

In this design, resistors are used for biasing the gate and the collector with a single supply while Caps are there to remove ripples of the supply I suppose.

L1 and L4 seems like RF chokes. Effect of L2 and L3 needs to be calculated if freq is known.