dft hold time violation problem

In the design, both of posedge and negedge of clock is used.
dc automatically insert test_si for negedge of clock, as shown below

but the log report hold time for test_si violate:

1. --------------------------------------------------------------------------
   
2. clock (input port clock) (rise edge)0.000.00
   
3. clock network delay (ideal)0.000.00
   
4. input external delay0.000.00 r
   
5. test_si2 (in)0.000.00 r
   
6. tposemem/test_si2 (tposemem_test_1)0.000.00 r
   
7. tposemem/Bisted_DPR64x16/test_si1 (Bisted_DPR64x16_test_1)
   
8. 0.000.00 r
   
9. tposemem/Bisted_DPR64x16/BistCtrl_i0/test_si1 (BistCtrl_DPR64x16_test_1)
   
10. 0.000.00 r
    
11. tposemem/Bisted_DPR64x16/BistCtrl_i0/S55/test_si (ST_MAG_DPR64x16_test_1)
    
12. 0.000.00 r
    
13. tposemem/Bisted_DPR64x16/BistCtrl_i0/S55/S5_reg[0]/SI (SDFFNHX8)
    
14. 0.000.00 r
    
15. data arrival time0.00
    
16. 
    
17. clock CLK (fall edge)10.0010.00
    
18. clock network delay (ideal)0.0010.00
    
19. tposemem/Bisted_DPR64x16/BistCtrl_i0/S55/S5_reg[0]/CKN (SDFFNHX8)
    
20. 0.0010.00 f
    
21. library hold time0.0510.05
    
22. data required time10.05
    
23. --------------------------------------------------------------------------
    
24. data required time10.05
    
25. data arrival time0.00
    
26. --------------------------------------------------------------------------
    
27. slack (VIOLATED)-10.05

复制代码

the slack is about half of clock period.
How to solve the problem? Need i constraint test_si?

问题在于在实际设计中你的TEST-SI是有CLK还是CLKN驱动?
即便是CLK，你可以用LOCKUP LATCH解决

>>Need i constraint test_si?
YEs you should defined it is triggered CLK or CLKN