Re: 65nm芯片，decap电容的加法有什么讲究么？
The decap cells are used as improve the IR drop in the digital design. But these capacitance will add more current in power line. So it is not true that more decap added, more improvement of IR drop is. There will be some EM issues from dynmaic point of view!!
So all these cases are on dynamic analysis. You need to run dynamic IR drop analysis and then annotation decap value, it will give a range of how many decap is needed. Then check dynamic EM, if it has more issue, you need to enlarge power line.
You can refer synopsys PrimeRail Guide to get more flow issue.
Anyway, for easy flow, add spare cell, then add decap before filler cells, (because common decap only has large size x32 x16 x8 x4). After that, add filler cell to fill up small gap in rows.
I do not use that method. The safe way is add more power mesh on the layout to reduce the EM issue. The average(static) EM will be one-third to one-fifth of Peak one. So it is save to give some margin on power plan.
For the decap leakage, it is also a issue. But this somehow enlarge the current density. Commonly, it is only <5% of total leakage. Consider the charge current of decap cell, there will be extra more current flow through power line in short period. Anyway, globally it keep constant.
I think decap and power mesh inductor will somehow have oscillation. But it is not a big issue. Resistor is main domination in power mesh. For current spectrum. it can be distributed from clock edge distribution. It will improve the subtract noise to analog circuit, especially for high speed design (>500MHz). For low speed, it is not a critical issue.
But it is good point to give some simulation on power mesh and decap oscillation. Just a good research field!