基于网络编码的多信源组播通信系统，包括源代码，原理图等

Input_fifo_empty_2

1

input

1=input FIFO is empty,0=otherwise

Input_fifo_rd_en_2

1

output

Read enable

Data_arbiter_ctrl_1

64

output

Output data bus to "control module"

Ctrl_arbiter_ctrl_1

8

Output

Output ctrl bus to "control module"

Val_arbitrer_ctrl_1

1

Output

1=data from input arbiter 1 to head splitter 1 is valid, 0=otherwise

Rdy_arbiter_ctrl_1

1

Input

1=module "head splitter 1" is ready to receive

Data_arbiter_ctrl_2

64

output

Output data bus to "control module"

Ctrl_arbiter_ctrl_2

8

Output

Output ctrl bus to "control module"

Val_arbitrer_ctrl_2

1

Output

1=data from input arbiter 2 to head splitter 2 is valid, 0=otherwise

Rdy_arbiter_ctrl_2

1

Input

1=module "head splitter 2" is ready to receive, 0=otherwise

Data_arbiter_out_1

64

output

Output data bus to "output arbiter module"

Ctrl_arbiter_out_1

8

Output

Output ctrl bus to "output arbiter module"

Val_arbiter_out_1

1

Output

1=data from input arbiter 1 to output arbiter is valid, 0=otherwise

Rdy_arbiter_out_1

1

Input

1=module "output arbiter" is ready to receive from input arbiter 1, 0=otherwise

Data_arbiter_out_2

64

output

Output data bus to "output arbiter module"

Ctrl_arbiter_out_2

8

Output

Output ctrl bus to "output arbiter module"

Val_arbiter_out_2

1

Output

1=data from input arbiter 2 to output arbiter is valid, 0=otherwise

Rdy_arbiter_out_2

1

Input

1=module "output arbiter" is ready to receive from input arbiter 2, 0=otherwise

clk

1

Input

System clock, running at 125MHz

Rst_n

1

input

System asynchronous reset signal

Sub module name

quantity

description

Head_spliter

2

Split head and payload, send head to "head info extractor", send payload to "FIFO ctrl payload"

Head_info_extractor

2

Receive head from "head splitte