微波EDA网,见证研发工程师的成长!
首页 > 通信和网络 > 通信网络技术文库 > 基于网络编码的多信源组播通信系统,包括源代码,原理图等

基于网络编码的多信源组播通信系统,包括源代码,原理图等

时间:11-08 来源:3721RD 点击:

1

output

Read enable

Router status

3

output

Output FSM state signal to "packing FIFO" and "packing center", coordinate with the control of packing procedure

Data_router_packingfifo

73

output

Output data bus to "packing FIFO". Bit 64 is set to "0" to indicate this is an uncoded packet

Wr_en_router_packingfifo

1

output

Write enable

Rdy_router_packingfifo

1

input

1=module "packing FIFO" is ready to receive from payload router, 0=otherwise

Empty_packingfifo

1

input

1=FIFO packing is empty,0=otherwise

Data_converter_packingfifo

73

output

Output data bus to "packing FIFO". Bit 64 is set to "1" to indicate this is a coded packet

Wr_en_converter_packingfifo

1

Output

Write enable

Rdy_converter_packingfifo

1

output

1=module "packing FIFO" is ready to receive from m72to64 converter, 0=otherwise

Empty_converterfifo

1

output

1=FIFO converter is empty,0=otherwise

Rand_num_1

8

output

Output random number 1 to "packing center"

Rand_num_2

8

output

Output random number 2 to "packing center"

clk

1

input

System clock running at 125MHz

Rst_n

1

input

System asynchronous reset signal

④ 功能描述及数据流

本模块为主运算模块。子模块paylaod router构建与上游模块control的接口,从control的子模块FIFO ctrl payload中读取数据。若两FIFO都非空,则说明control模块同时处理了两条通道,也即需要进行编码操作。Paylpad router同时读取两个FIFO中的数据,送往由m64×8 multiplier、m72×72 adder以及m72to64 converter组成的"编码流水线"进行编码运算,并向下游packing模块发送编码过的数据包。

子模块prng tap16是8位伪随机数产生器。使能信号rand_num_en有效时,产生一个8位伪随机数。子模块m64×8 multiplier是64乘8位乘法器,该模块将负载与随即系数相乘,得到72位结果。m72×72 adder是72位全加器,将两个乘法器得到的结果相加得到编码输出。m72to64 converter是位宽转换器,由于coding模块输出的数据总线仍需保持64位,所以需要该转换器将72位编码输出转换为64为编码数据。由于是同步电路,采用同一时钟,该位宽转换将产生一定的数据囤积,需要较大缓存。

⑤ 关键时序与状态机

Payload router状态机

图3.2-7 Payload router状态机

4、Packing

① 子模块列表

Sub module name

quantity

Description

Packing FIFO

1

Receive and store processed packets before being packed in "packing center"

Packing center

1

Packing payload with all sorts of heads

② 内部结构图

图3.2-8 Packing内部结构图

③ 本模块输入输出信号列表及说明

Signal name

Bit width

I/O

Description

Data_router_packingfifo

73

input

Input data bus from "payload router". Bit 64 is set to "0" to indicate this is an uncoded packet

Wr_en_router_packingfifo

1

Input

Write

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top