基于网络编码的多信源组播通信系统，包括源代码，原理图等

if no address matches, then check the decode factor2 */

GET_FACTOR1_RESLT: begin

state_next = RD_DRAM_MINOR_STEP;

cam_lookup_reslt_next = cam_lookup_reslt | {match_2,match_1,match_0};

cam_lookup_reslt_pre_next = cam_lookup_reslt | {match_2,match_1,match_0};

if(match_2) begin

match_addr_temp_2_next = match_addr_2;

end

if(match_1) begin

match_addr_temp_1_next = match_addr_1;

end

if(match_0) begin

match_addr_temp_0_next = match_addr_0;

end

end

RD_DRAM_MINOR_STEP:

if(rd_idle)

if(|cam_lookup_reslt) begin

state_next = LUP_DCOD_FACTOR1_FIRST;

if(cam_lookup_reslt==3'b001)

begin

addr_vld = 1;

block_num_rd = match_addr_temp_0;

port_num_rd = 2'b00;

cam_lookup_reslt_next=0;

end

else if (cam_lookup_reslt==3'b010)

begin

addr_vld = 1;

block_num_rd = match_addr_temp_1;

port_num_rd = 2'b01;

cam_lookup_reslt_next=0;

end

else if (cam_lookup_reslt==3'b100)

begin

addr_vld = 1;

block_num_rd = match_addr_temp_2;

port_num_rd = 2'b10;

cam_lookup_reslt_next=0;

end

end

else

begin

state_next = LUP_DCOD_FACTOR2;

pkt_not_find = 1;

has_other_factor = has_factor2;

end

/* decoding the packet by decode factor2 */

LUP_DCOD_FACTOR2:

if(has_factor2) begin

addr_vld = 1;

block_num_rd = other_dram_addr;

port_num_rd = other_port_num_rd;

state_next = LUP_DCOD_FACTOR1_FIRST;

cam_lookup_reslt_pre_next = cam_lookup_reslt_save;

has_factor2_next = 0;

end

else begin

pkt_not_find = 1;

has_other_factor = has_factor2;

state_next = GET_SRC_GEN_NUM;

end

endcase // case(state)

end // always @ (*)

always @(posedge clk) begin

src_num_sel <= `DLY src_num_sel_next;

gen_num_sel <= `DLY gen_num_sel_next;

cam_lookup_reslt_pre <= `DLY cam_lookup_reslt_pre_next;

other_dram_addr <= `DLY other_dram_addr_next;

other_port_num_rd <= `DLY other_port_num_rd_next;

match_addr_temp_2 <= `DLY match_addr_temp_2_next;

match_addr_temp_1 <= `DLY match_addr_temp_1_next;

match_addr_temp_0 <= `DLY match_addr_temp_0_next;

cam_lookup_reslt_save <= `DLY cam_lookup_reslt_save_next;

end

always @(posedge clk or negedge rst_n) begin

if(rst_n == 1'b0) begin

state <= IDLE;

src_num <= 0;

gen_num <= 0;

has_factor2 <= 0;

cam_lookup_reslt <= 0;

couter <= 5'b0;

end

else begin

state <= `DLY state_next;

src_num <= `DLY src_num_next;

gen_num <= `DLY gen_num_next;

couter <= `DLY couter_next;

cam_lookup_reslt <= `DLY cam_lookup_reslt_next;

has_factor2 <= `DLY has_factor2_next;

end

end

endmodule //decode_control_sm