基于网络编码的多信源组播通信系统，包括源代码，原理图等

GET_BOTH: begin

first_dword_2 <= 0; //

val_router_multiplier_2 <= 0; //clear valid signal

//read-FIFO-delay

if (counter_getdata < 2'b01) begin

counter_getdata <= counter_getdata + 1;

router_status <= GET_BOTH;

rd_en_payloadfifo_router_1 <= 0;

rd_en_payloadfifo_router_2 <= 0; //clear rd_en signals

end

else begin

data_temp1 <= data_payloadfifo_router_1;

ctrl_temp1 <= ctrl_payloadfifo_router_1;

data_temp2 <= data_payloadfifo_router_2;

ctrl_temp2 <= ctrl_payloadfifo_router_2;

router_status <= SEND_BOTH_1;

end

end //state GET_BOTH ends

//according to the random number generator, data from both

//input channels should be sent out seperately

SEND_BOTH_1: begin

if (!rdy_router_multiplier_1) begin

val_router_multiplier_1 <= 0;

router_status <= SEND_BOTH_1;

end

else begin

data_router_multiplier_1 <= data_temp1;

val_router_multiplier_1 <= 1;

if (ctrl_temp1 == 8'hff) begin

first_dword_1 <= 1;

rand_num_en <= 1;

end

else begin

first_dword_1 <=0;

rand_num_en <= 0;

end

router_status <= SEND_BOTH_2;

end

end //state SEND_BOTH_1 ends

SEND_BOTH_2: begin

first_dword_1 <= 0;

val_router_multiplier_1 <= 0; //clear valid signal

//confirm the first random number is generated successfully

//before enable to generate the second.

if (ctrl_temp1 == 8'hff) begin

if (!rand_num_val) begin

rand_num_en <= 0;

router_status <= SEND_BOTH_2;

end

end

else begin

if (!rdy_router_multiplier_2) begin

val_router_multiplier_2 <= 0;

router_status <= SEND_BOTH_2;

end

else begin

data_router_multiplier_2 <= data_temp2;

val_router_multiplier_2 <= 1;

if (ctrl_temp2 == 8'hff) begin

first_dword_2 <= 1;

rand_num_en <= 1;

end

else begin

first_dword_2 <= 0;

rand_num_en <= 0;

end

if (((ctrl_temp1 == 8'hf0) && (& (ctrl_temp2))) || ((ctrl_temp2 == 8'hf0) && (& (ctrl_temp1)))) begin

router_status <= JUDGE;

end

else begin

rd_en_payloadfifo_router_1 <= 1;

rd_en_payloadfifo_router_2 <= 1;

counter_getdata <= 0;

router_status <= GET_BOTH;

end

end

end

end //state SEND_BOTH_2 ends

endcase

end

end

endmodule

附2：解码路由器核心代码之一：解码控制模块：decode_control_sm. v

///////////////////////////////////////////////////////////////////////////////

// vim:set shiftwidth=3 softtabstop=3 expandtab:

// Copyright(c) 2009, All rights reserved.

// Advanced Network technology Lab, Shenzhen graduated school of PKU

// Module: decode_control_sm.v

// Project: NF2.1

// Time and Author: 2009-12-15 zhang ming long

// Description: According to the pkts' source and generation sequence number,

// this module goes round-robin strategy to control the module decoder

// to decode the pkts stored in DRAMS.

///////////////////////////////////////////////////////////////////////////////

`define DLY #1

`timescale 1ns/1ps

module decode_control_sm

#(parameter SRC_WIDTH = 4,

pa