基于网络编码的多信源组播通信系统，包括源代码，原理图等

//payload fifo 2 port

input [DATAWIDTH - 1:0] data_payloadfifo_router_2,

input [CTRLWIDTH - 1:0] ctrl_payloadfifo_router_2,

input empty_payloadfifo_router_2,

output reg rd_en_payloadfifo_router_2,

//multiplier 1 port

input rdy_router_multiplier_1,

output reg [DATAWIDTH - 1:0] data_router_multiplier_1,

output reg first_dword_1, //flag to indicate the start of a pkt. only when it is the first double word of a pkt, should the random number be updated.

output reg val_router_multiplier_1,

//multiplier 2 port

input rdy_router_multiplier_2,

output reg [DATAWIDTH - 1:0] data_router_multiplier_2,

output reg first_dword_2, //flag to indicate the start of a pkt. only when it is the first double word of a pkt, should the random number be updated.

output reg val_router_multiplier_2,

//rand number generator port

output reg rand_num_en, //enable the random number generator

input rand_num_val,

//packing fifo port

input rdy_router_packingfifo,

input empty_packingfifo, // only when the whole last pkt is sent out, and the packing fifo is empty, then proceed the next pkt

output reg [DATAWIDTH + CTRLWIDTH:0] data_router_packingfifo, //an extra bit(MSB) to indicate whether it is a coded pkt

output reg val_router_packingfifo,

output reg [2:0] router_status, //send router_status to packing_fifo, indicate where to get data

//misc

input clk,

input rst_n

);

reg [DATAWIDTH - 1:0] data_temp1;

reg [CTRLWIDTH - 1:0] ctrl_temp1;

reg [DATAWIDTH - 1:0] data_temp2;

reg [CTRLWIDTH - 1:0] ctrl_temp2;

reg [1:0] counter_getdata; //counter for the read-FIFO-delay, 1 clock circle

parameter JUDGE = 3'b000;

parameter GET_DATA2 = 3'b001;

parameter SEND_DATA2 = 3'b010;

parameter GET_DATA1 = 3'b011;

parameter SEND_DATA1 = 3'b100;

parameter GET_BOTH = 3'b101;

parameter SEND_BOTH_1 = 3'b110;

parameter SEND_BOTH_2 = 3'b111;

always @(posedge clk or negedge rst_n) begin

//reset process

if (rst_n == 0) begin

router_status <= JUDGE;

data_temp1 <= 64'h0;

ctrl_temp1 <= 8'h0;

data_temp2 <= 64'h0;

ctrl_temp2 <= 8'h0;

counter_getdata <= 2'b0;

end

else begin

case (router_status)

JUDGE: begin

first_dword_1 <= 0;

first_dword_2 <= 0;

rand_num_en <= 0;

val_router_multiplier_2 <= 0; //clear some signals

//program hold, when packing FIFO inempty

if (!empty_packingfifo) begin

router_status <= JUDGE;

end

else begin

//both FIFO ctrl payload 1 & 2 are empty

if (empty_payloadfifo_router_1 && empty_payloadfifo_router_2) begin

rd_en_payloadfifo_router_1 <= 0;

rd_en_payloadfifo_router_2 <= 0;

router_status <= JUDGE;

end

//FIFO ctrl paylaod 2 is inempty, read from this FIFO,

//coding will be unnecessary

else if (empty_payloadfifo_route