基于网络编码的多信源组播通信系统，包括源代码，原理图等

Rdy_router_packingfifo

1

Output

1=module "packing FIFO" is ready to receive from payload router, 0=otherwise

Router_status

3

input

Input FSM state signal to coordinate with the control of "packing FIFO"

Empty_packingfifo

1

output

1=FIFO packing is empty,0=otherwise

Data_converter_packingfifo

73

input

Input data bus from "m72to64 converter". Bit 64 is set to "1" to indicate this is a coded packet

Wr_en_converter_packingfifo

1

Input

Write enable

Rdy_converter_packingfifo

1

Output

1=module "packing FIFO" is ready to receive from m72to64 converter, 0=otherwise

Empty_converterfifo

1

Input

1=FIFO converter is empty,0=otherwise

Data_center_legacyfifo_1

64

Input

Input data bus from "FIFO ctrl legacy 1"

Rd_en_center_legacyfifo_1

1

output

Read enable

Data_center_packinginfo_1

14

Input

Input data bus from "FIFO ctrl packinginfo 1"

Rd_en_center_packinginfo_1

1

output

Read enable

Data_center_legacyfifo_2

64

Input

Input data bus from "FIFO ctrl legacy 2"

Rd_en_center_legacyfifo_2

1

output

Read enable

Data_center_packinginfo_2

14

Input

Input data bus from "FIFO ctrl packinginfo 2"

Rd_en_center_packinginfo_2

1

output

Read enable

Rand_num_center_1

8

input

Input random number from "m64×64 multiplier 1"

Rand_num_center_2

8

input

Input random number from "m64×64 multiplier 2"

Out_data_out_0

64

output

Output data bus to "output arbiter"

Out_ctrl_out_0

8

Output

Output ctrl bus to "output arbiter"

Data_val_out_0

1

Output

1=data from packing center to output arbiter is valid, 0=otherwise

Rdy_out_0

1

Input

1=output arbiter is ready to receive from packing center, 0=otherwise

clk

1

Input

System clock running at 125 MHz

Rst_n

1

input

System asynchronous reset signal