phase locked loops about dejitter

Hi, all friends

In one of my design, I received the master station' PSK waveform and the data clock had been recoveried. But the recoveried data clock do not meet the system requirement. The clock outpout from the demodulator must be very low phase noise,say, 130dBc/Hz at 100Hz.

So, I use a second phase locked loop and a low phase noise OCVCXO to retiming the received clock. But i donot know what kind of phase detector should i use.

ADF series or LMX series frequency synthesizer chips can be used for design frequency synthesizer, but these edge type detectors may be not suit for the case the reference clock is not high S/N.

Is the EXCLUSIVE-OR gate type detector more fitable? The problem is that except HC4046, there are not other high performance phase detector chips for business use.

Or, i had to use a CPLD chip to design the phase detector?

Thanks

Most people just square up the low frequency sine wave with a logic gate. The ACT family of cmos is a low phase noise gate.

Hi,
Besides the logic gate, are there any other phase detctor available? what i know is only hc4046 and ne56x series.
thanks

Peregrine Semi does have some nice PLL/phase dectector chips.... look at w*w.psemi.com
or, maybe you could simply use a linear type of
phase detector, like a balanced ringdiode mixer. These are very low-noise too!

/WebDog

Hi,
When i use exclusive-OR gate type detector, the loop is easy to be in locked, but use the edge type FPD, the loop is very difficult to be in locked and the jitter of the output waveform is big.

could some friends explain it?

thanks