PhaseLocked Loop Problem
时间：04-06
整理：3721RD
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Hello Everyone,
i am designing a simple phase locked loop with only CMOS chips CD 4007, i have built it before and worked fine. however i did something wrong to make it work. now i am reassembling it and i was not able to get it work. i am using an XOR for my phase detector , i tried using both a passive RC filter and a passive lead lag RC filter , i am using a 7 staged ring oscillator as my VCO. i am getting an unstable signal. with both sine and square waves as reference signals [ 1 ~ 100 khz ] [ 1.8v-5v]. i know that i dont have to use a frequency divider since i want it to lock not multiply. so would some one help me if i am missing any main block.
i am designing a simple phase locked loop with only CMOS chips CD 4007, i have built it before and worked fine. however i did something wrong to make it work. now i am reassembling it and i was not able to get it work. i am using an XOR for my phase detector , i tried using both a passive RC filter and a passive lead lag RC filter , i am using a 7 staged ring oscillator as my VCO. i am getting an unstable signal. with both sine and square waves as reference signals [ 1 ~ 100 khz ] [ 1.8v-5v]. i know that i dont have to use a frequency divider since i want it to lock not multiply. so would some one help me if i am missing any main block.
A poster had a thread here describing how he saw two oscillators synchronize if their frequencies were close enough, and there was the right kind of connection between them.
Apparently there needs to be sufficient crosstalk between the two signals so that one can influence the other. Barely enough so they synchronize when they are within a few Hz of each other.
Try looking at similar threads in the list at the bottom of this page.