why not phase locked loop for BPSK?
I fear you're asking too general for a meaningful answer. In some cases, BPSK will be demodulated by a PLL directly, in most cases complex receiver topologies give better performance. We should refer to specific receiver scenarios to discuss it.
Okay, more specifically, text books claim that the matched filter (multiplying by the source oscillator) is the optimal way to decode a BPSK signal in the presence of noise.
It seems that a PLL which is just trying to lock onto the phase of the BPSK signal near a certain frequency, would be more optimal. It is amplitude independent.
Thoughts?
BPSK can use various types of demodulators, and PLL is just one of them.
Yes. I know this. But the matched filter for BPSK does not use a PLL, and the matched filter is supposed to be optimal. I am asking if anyone has an explanation for this.
If you send a repeat of zeros, the PLL will try to lock to this, and when a 1 comes along, you get an output, then if a string of 1s come along the output will fall and not give an output until a 0 comes along. It would be like AC coupling the digital signal through a capacitor, where when the mean DC level shifts some 0s or 1s might get lost.
Frank