Re: Phase locked loop based FM transmitter

I think any divide-by-N should be fine if it can support the frequency. There are some PLL ics that will contain that, plus the phase detector, see Analog Devices. However most will be surface mount.

My supervisor asked to design a programmable divide by N counter instead of using a programmable divided by n counter in a PLL chip. Any help to design a divided by N counter would be a great help to me. :) My transmitter has to has 200 channels with 100 kHz steps from 88MHz to 108MHz.

guys please help..

Do you mean that you have to replace the 74HC4059 chip with discrete chips? One way to go would be is to first of all use a fast divide by 10 as a prescaler, to get the frequency down to 8.8 -> 10.8 MHZ. follow this by three divide by 10 BCD counters. Each of these will have a BCD output (ABCD) which you can then decode into decimal outputs (0....9). Each of these decade outputs then go to a rotary switch (3 off) so any digit can be selected. All the "selected" digits are then ANDed together and used to reset all the counters. The reset pulse will then occur at 100 KHZ which you can use to compare with a reference 100KHZ derived from a crystal oscillator in a phase locked loop back to the 88-108 VCO.
Frank

Tnx for the reply.
Hmm... I don't want to use the 74HC4059 chip. I already chose the MAX2606 as the VCO and if the programmable divided by N counter can be designed in the FM broadcasting band it would be great coz I can forget the errors occurs from a prescaler. But I was unable to find chips that are working in 88MHz-108MHz to design a programmable divided by N counter. Dividing by 10 for prescaling is giving lesser accuracy. I like to divide it by 2 which gives the freq. range in 44MHz - 54MHz. If still it is not possible to find chips to design a programmable divided by N counter then I would go with divided by 4 scaler.

So, first I want to design a suitable programmable divided by N counter working within 44MHz-54MHz. Any help to to design such a divided by N counter would be great.

Anyway I am still struggling to design a programmable divided by N counter. I have less knowledge in designing a suitable programmable counter for my project.

I've used the Sanyo LM7001 in the past but I'm not sure if it's still available. It's programmable and works directly at up to 130MHz.

Brian.

Hi!
I want to design a programmable divided by N counter. Not to use a divided by N counter chip.

I think, a solution has been sketched in post #25. Did you understand it?

Not much.
Anyway, I found the BCD decade up/down counter 74F190 with asynchronous presetting which has a typical count freq. of 125MHz. If I use this I don't need a prescaler and it can be cascaded. I think I can use it to build my programmable divided by N counter for my project. However, I need your opinions and suggestions about by my current choice for the programmable divided by N counter.
I think I can design the counter using 74F190 according to Chuckey's directions. Isn't it?

It don't think that 47F190 works for this design. You'll need a counter with synchronous carry to achieve multiple digit decimal preset operation. The last when I implemented a similar function (decimal frequency divider), I used a CPLD.

I have lack knowledge about this divided by N counter designing. How multiple digital operation can be done by synchronous carry? Any good references to study about this?
Using a CPLD will increases my cost significantly for the project.
Do you know any suitable decade counter this programmable divided by N counter design? If there is no suitable counter in this frequency range (88MHz - 108 MHz) please let me know at least any decade counter with counting freq. between 44MHz - 54MHz to use with a prescaler.

Guys.. I need your help..

Any opinions or suggestions about this diagram of the circuit? (Forgot to include the low pass filter in the diagram )