clock gating
但不知道為什麼switch power變高了?
照理說合成clock gating後，power要下降
但我完全反過來，請問這是什麼原因造成的?
report有点问题吧，贴出来看看
current_design [get_designs Reg1_32bit]
Current design is 'Reg1_32bit'.
{Reg1_32bit}
insert_clock_gating
Warning: Clock gating insertion with insert_clock_gating is deprecated and will be removed in a future release; instead use the compile -gate_clock command. (PWR-729)
Information: Performing clock-gating on design Reg1_32bit
# Latch based CG (default)
set_clock_gating_style -sequential_cell latch
Current clock gating style....
Sequential cell: latch
Minimum register bank size: 3
Minimum bank size for enhanced clock gating: 6
Maximum fanout: unlimited
Setup time for clock gate: 0.000000
Hold time for clock gate: 0.000000
Clock gating circuitry (positive edge): and
Clock gating circuitry (negative edge): or
Note: inverter between clock gating circuitry
and (negative edge) register clock pin.
Control point insertion: none
Control signal for control point: scan_enable
Observation point insertion: false
Observation logic depth: 5
1
# Latch free CG
set_clock_gating_style -sequential_cell none
Warning: Using scan_enable with latch-free clock gating may cause DRC violations during test insertion. (PWR-379)
Current clock gating style....
Sequential cell: none
Minimum register bank size: 3
Minimum bank size for enhanced clock gating: 6
Maximum fanout: unlimited
Setup time for clock gate: 0.000000
Hold time for clock gate: 0.000000
Clock gating circuitry (positive edge): or
Clock gating circuitry (negative edge): and
Note: inverter between clock gating circuitry
and (negative edge) register clock pin.
Control point insertion: none
Control signal for control point: scan_enable
Observation point insertion: false
Observation logic depth: 5
1
# integrated CG
set_clock_gating_style -negative_edge_logic "integrated"
Error: The library cell required for use as an integrated clock-gating cell does not exist in the libraries specified.The required attribute is latch_negedge.(PWR-191)
Warning: The clock-gating style was not changed. (PWR-132)
Current clock gating style....
Sequential cell: none
Minimum register bank size: 3
Minimum bank size for enhanced clock gating: 6
Maximum fanout: unlimited
Setup time for clock gate: 0.000000
Hold time for clock gate: 0.000000
Clock gating circuitry (positive edge): or
Clock gating circuitry (negative edge): and
Note: inverter between clock gating circuitry
and (negative edge) register clock pin.
Control point insertion: none
Control signal for control point: scan_enable
Observation point insertion: false
Observation logic depth: 5
0
#set multi stages clock gating
set_clock_gating_style -num_stages 2 -sequential_cell latch
Current clock gating style....
Sequential cell: latch
Minimum register bank size: 3
Minimum bank size for enhanced clock gating: 6
Maximum fanout: unlimited
Setup time for clock gate: 0.000000
Hold time for clock gate: 0.000000
Clock gating circuitry (positive edge): and
Clock gating circuitry (negative edge): or
Note: inverter between clock gating circuitry
and (negative edge) register clock pin.
Control point insertion: none
Control signal for control point: scan_enable
Observation point insertion: false
Observation logic depth: 5
Maximum number of stages: 2
------------------------------------------------------------------------------
以上是我的report，請幫我看看，有點不太了解錯在哪裡?
report_power出来看看
学习了
power cell本身也是带free run 的clock的，看你cg结构设计如何，不是说加上一定省电的。
谢谢。
dc报power就是个笑话，cg的activity标不上去的