how can power or ground bump connect to PG network

for flip chip, I'm a newer, some questions to ask.
1.how can power or ground bump connects to PG network
is it like this: power bump -> power IO buffer -> internal PG network
can power/ground bump connects to internal PG network directly, for example, connect top metal to bump by RV (between top metal and APRDL)?
or power /ground bump connects to a core ESD cell first and then to internal PG?
2.another question, for flip chip, there is build-up substrate and laminate substrate?
does anyone know what it is?
Thanks,

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1. for flip chip, you can connect core P/G bump to top metall by RV directly, not need to connect to ESD cell;
2. for build-up substrate and laminate substrate, these substrate type are determined by package, can affect bump size and minimum bump pitch.
that's all.

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1. for flip chip, you can connect core P/G bump to top metall by RV directly, not need to connect to ESD cell;
2. for build-up substrate and laminate substrate, these substrate type are determined by package, can affect bump size and minimum bump pitch.
that's all.