soc 中关于create_generated_clock引起的error求助？
时间：10-02
整理：3721RD
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SOC Encounter中碰到的error，导致SOC Encounter不能routing，place倒是没问题。但是开始place的时候也会弹出类似的error。
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR2' at source pin 'display/fr2_reg/Q' to the 'Rise' edge of generated clock 'FR4' at pin 'display/fr4_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR4'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR2' at source pin 'display/fr2_reg/Q' to the 'Fall' edge of generated clock 'FR4' at pin 'display/fr4_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR4'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR4' at source pin 'display/fr4_reg/Q' to the 'Rise' edge of generated clock 'FR8' at pin 'display/fr8_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR8'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR4' at source pin 'display/fr4_reg/Q' to the 'Fall' edge of generated clock 'FR8' at pin 'display/fr8_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR8'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
Gatelevel 网表是这样的：
DFFRBX1 fr2_reg ( .D(n198), .CKB(fr), .RB(n255), .Q(fr2) );
DFFRBX1 fr4_reg ( .D(n199), .CKB(fr2), .RB(n255), .Q(fr4) );
DFFRBX1 fr8_reg ( .D(n200), .CKB(fr4), .RB(n255), .Q(fr8) );
SDC中FR4和FR8的设置：
create_generated_clock -name FR4 -source [get_pins {display/fr2_reg/Q}]\
-divide_by 2-add -master_clock [get_clocks {FR2}] [get_pins \
{display/fr4_reg/Q}]
create_generated_clock -name FR8 -source [get_pins {display/fr4_reg/Q}]\
-divide_by 2-add -master_clock [get_clocks {FR4}] [get_pins \
{display/fr8_reg/Q}]
set_clock_uncertainty2 [get_clocks {FR8}]
有谁知道怎么处理吗?PT没有报任何错误啊！
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR2' at source pin 'display/fr2_reg/Q' to the 'Rise' edge of generated clock 'FR4' at pin 'display/fr4_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR4'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR2' at source pin 'display/fr2_reg/Q' to the 'Fall' edge of generated clock 'FR4' at pin 'display/fr4_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR4'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR4' at source pin 'display/fr4_reg/Q' to the 'Rise' edge of generated clock 'FR8' at pin 'display/fr8_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR8'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
**ERROR: (TA-152):A latency path from the 'Rise' edge of the master clock 'FR4' at source pin 'display/fr4_reg/Q' to the 'Fall' edge of generated clock 'FR8' at pin 'display/fr8_reg/Q' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'FR8'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
Gatelevel 网表是这样的：
DFFRBX1 fr2_reg ( .D(n198), .CKB(fr), .RB(n255), .Q(fr2) );
DFFRBX1 fr4_reg ( .D(n199), .CKB(fr2), .RB(n255), .Q(fr4) );
DFFRBX1 fr8_reg ( .D(n200), .CKB(fr4), .RB(n255), .Q(fr8) );
SDC中FR4和FR8的设置：
create_generated_clock -name FR4 -source [get_pins {display/fr2_reg/Q}]\
-divide_by 2-add -master_clock [get_clocks {FR2}] [get_pins \
{display/fr4_reg/Q}]
create_generated_clock -name FR8 -source [get_pins {display/fr4_reg/Q}]\
-divide_by 2-add -master_clock [get_clocks {FR4}] [get_pins \
{display/fr8_reg/Q}]
set_clock_uncertainty2 [get_clocks {FR8}]
有谁知道怎么处理吗?PT没有报任何错误啊！
edi和pt 的理解不一样
edi不是告诉你了么 把 'timing_enable_genclk_edge_based_source_latency' 设成false即可
set_global
这样做的意义是什么?为什么要这么设置啊?不懂，求教！
试试不用"-divide_by 2"， 用“-edges {1 3 5}”
有什么区别吗?
有些generated clock的edge没法从master clock的定义里面找到或者derive出来
建议看看generated clock的定义问题，