关于pr后No clock-gating check等若干问题的警告
时间：10-02
整理：3721RD
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各位前辈，小弟刚做完布局布线，然后用pt读入spef文件进行分析，得到如下若干警告，请问该如何处理?分析应该是DC综合时候少写了什么。应该在DC中添加什么约束呢?
1.Warning: No clock-gating check is inferred for clock clk_d （其中clk_d是通过clk generate出来的）
2，Warning: The drive-resistance for the timing arc
(scadv10_cln65gp_rvt_ff_1p1v_0c/BUFHX16MA10TR) clk_rx__L1_I0/A-->Y (min rising & falling positive_unate)
is much less than the network impedance to ground;
PrimeTime has adjusted the drive-resistance to improve accuracy.
(RC-009)
1.Warning: No clock-gating check is inferred for clock clk_d （其中clk_d是通过clk generate出来的）
2，Warning: The drive-resistance for the timing arc
(scadv10_cln65gp_rvt_ff_1p1v_0c/BUFHX16MA10TR) clk_rx__L1_I0/A-->Y (min rising & falling positive_unate)
is much less than the network impedance to ground;
PrimeTime has adjusted the drive-resistance to improve accuracy.
(RC-009)
1.如果是mux，静态切换也可以不管。不是的话，要chk
2.可以不管
多谢您的解答！