关于icc使用中create_mw_lib的若干问题
时间：10-02
整理：3721RD
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菜鸟刚开始学习使用icc，尝试着跟着student user guide做每一步任务，在使用icc过程中create_mw_lib后遇见了许多自己无法解决的问题，发帖在此求助，希望各位高手能够指点我一下，不甚感激！
1.我所书写的tcl命令如下
set MW_lib {/home/wtt/test/CIC/pt/lib/smic18}
set search_path {search_path + /EDATools/SMIC/SMIC_018um_HOME/aci/sc-m/synopsys +/EDATools/SMIC/SMIC_018um_HOME/aci/sc-m/map + /EDAVendor/Synopsys/DC-2010.03-SP1/libraries/syn +/EDATools/SMIC/SMIC_018um_HOME/aci/sc-x/tlf + ../in + ../io + ./script + ../lib + $MW_lib}
set link_library [list ff_1v98_0c.db ff_1v98_m40c.db ss_1v62_125c.db tt_1v8_25c.db]
set target_library [list tt_1v8_25c.db ss_1v62_125c.db ff_1v98_0c.db ff_1v98_m40c.db]
set symbol_library [list smic18m.sdb]
create_mw_lib design_cic -open \
-technology {../lib/smic18_6lm.tf} \
-mw_reference_library {/home/wtt/test/CIC/pt/lib/smic18}
set_check_library_options -all
check_library
set_tlu_plus_files \
-max_tluplus fast.tlf \
-min_tluplus slow.tlf \
-tech2itf_map streamOut.map
check_tlu_plus_files
read_verilog -dirty_netlist ../in/cic_top.v
current_design CIC_TOP
check_design
uniquify
link
save_mw_cel -as CIC_TOP
list_libs
exit
2.在load tf文件时候出现了如下的warning,请问这是否需要引起重视呢?
Start to load technology file ../lib/smic18_6lm.tf.
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 480) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 498) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 516) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 534) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 552) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology file ../lib/smic18_6lm.tf has been loaded successfully.
3.在开始check library 后出现这样的一句话，是否是我设置mw没有成功呢?
#BEGIN_XCHECK_LOGICCELLS
All 478 physical cells in design_cic are missing in logic library.
/home/wtt/test/CIC/pt/lib/smic18 are missing in logic library.
#END_XCHECK_LOGICCELLS
#BEGIN_XCHECK_PHYSICALCELLS
All 2472 logic cells in ff_1v98_0c
ff_1v98_m40c
ss_1v62_125c
tt_1v8_25c
are missing in physical library.
#END_XCHECK_PHYSICALCELLS
4. check library时候的一个error, 我没有看明白是什么意思，请大家指导，谢谢！
#BEGIN_CHECK_PHYSICALPROPERTY
Total number of cells:
0
Information: List of main and reference libraries(LIBCHK-120)
----------------------------------------------------------------------------------
Library namePathUnit tileTile size
----------------------------------------------------------------------------------
design_cic/home/wtt/test/CIC/pt/scriptunit0.660x5.040
smic18/home/wtt/test/CIC/pt/libunit0.660x5.040
----------------------------------------------------------------------------------
List of tile patterns
---------------------------------------------------------------------------------
Tile patternUnit tileLocationOrientationTile size
---------------------------------------------------------------------------------
No tile pattern
---------------------------------------------------------------------------------
Information: List of routing properties(LIBCHK-122)
Unit tile : unitTile
-----------------------------------------------------------------------
PreferredTrack
LayerdirectiondirectionOffsetPitchRemarks
-----------------------------------------------------------------------
METAL1HH0.2800.560OK
METAL2VV0.3300.660OK
METAL3HH0.2800.560OK
METAL4VV0.3300.660OK
METAL5HH0.2800.610offset=0.46pitch
METAL6VV0.3300.950offset=0.35pitch
-----------------------------------------------------------------------
Error: Mismatched and missing data found. Please refer to LIBCHK-122.(LIBCHK-101)
#END_CHECK_PHYSICALPROPERTY
5. check library中的 check tech项遇见很多warning, 也不明白是什么意思，同求指导
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 582) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 582) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 582) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 600) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 618) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 636) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 654) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology data checked and saved in Milkyway log file.
Dumped tech file is design_cic.tf_checker
Logic vs. logic library check summary:
Warning: Library 'ff_1v98_0c(lib#1)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'ff_1v98_0c(lib#1)' is missing CCS receiver models.(LIBCHK-332)
Warning: Library 'ff_1v98_m40c(lib#2)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'ff_1v98_m40c(lib#2)' is missing CCS receiver models.(LIBCHK-332)
Warning: Library 'ss_1v62_125c(lib#3)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'ss_1v62_125c(lib#3)' is missing CCS receiver models.(LIBCHK-332)
Warning: Library 'tt_1v8_25c(lib#4)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'tt_1v8_25c(lib#4)' is missing CCS receiver models.(LIBCHK-332)
Information: Logic library inconsistencies found for MCMM.(LIBCHK-360)
Information: Logic library inconsistencies found for UPF.(LIBCHK-361)
Information: Logic library inconsistencies found for CCS timing scaling.(LIBCHK-362)
Information: Logic library inconsistencies found for CCS noise scaling.(LIBCHK-362)
Logic library consistency check PASSED for power scaling.
6. 在导入verilog 设计后出现许多undefined module，麻烦大神们给我解释解释吧！
Compiling source file /home/wtt/test/CIC/pt/in/cic_top.v
Warning: Cell 'ADDHX1M.CEL' is created for undefined module 'ADDHX1M'. (MWNL-294)
Warning: Cell 'XOR2X1M.CEL' is created for undefined module 'XOR2X1M'. (MWNL-294)
Warning: Cell 'CLKINVX1M.CEL' is created for undefined module 'CLKINVX1M'. (MWNL-294)
Warning: Cell 'NOR2X1M.CEL' is created for undefined module 'NOR2X1M'. (MWNL-294)
7.导入design后，命令check design,uniquify出现logic cell在physical library 里面不匹配的warning, 然后出现error
Information: linking reference library : /home/wtt/test/CIC/pt/lib/smic18. (PSYN-878)
Warning: The 'XOR2XL' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Warning: The 'XOR2X4' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Warning: The 'XOR2X2' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Warning: The 'XOR2X1' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Error: The design is not uniquified. (MWDC-101)
# GUI Debug: Building dc from empty. -- Time: 562ms
Error: Fail to rebuild timing design from database (UID-841)
0
1.我所书写的tcl命令如下
set MW_lib {/home/wtt/test/CIC/pt/lib/smic18}
set search_path {search_path + /EDATools/SMIC/SMIC_018um_HOME/aci/sc-m/synopsys +/EDATools/SMIC/SMIC_018um_HOME/aci/sc-m/map + /EDAVendor/Synopsys/DC-2010.03-SP1/libraries/syn +/EDATools/SMIC/SMIC_018um_HOME/aci/sc-x/tlf + ../in + ../io + ./script + ../lib + $MW_lib}
set link_library [list ff_1v98_0c.db ff_1v98_m40c.db ss_1v62_125c.db tt_1v8_25c.db]
set target_library [list tt_1v8_25c.db ss_1v62_125c.db ff_1v98_0c.db ff_1v98_m40c.db]
set symbol_library [list smic18m.sdb]
create_mw_lib design_cic -open \
-technology {../lib/smic18_6lm.tf} \
-mw_reference_library {/home/wtt/test/CIC/pt/lib/smic18}
set_check_library_options -all
check_library
set_tlu_plus_files \
-max_tluplus fast.tlf \
-min_tluplus slow.tlf \
-tech2itf_map streamOut.map
check_tlu_plus_files
read_verilog -dirty_netlist ../in/cic_top.v
current_design CIC_TOP
check_design
uniquify
link
save_mw_cel -as CIC_TOP
list_libs
exit
2.在load tf文件时候出现了如下的warning,请问这是否需要引起重视呢?
Start to load technology file ../lib/smic18_6lm.tf.
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 480) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 498) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 516) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 534) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 552) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology file ../lib/smic18_6lm.tf has been loaded successfully.
3.在开始check library 后出现这样的一句话，是否是我设置mw没有成功呢?
#BEGIN_XCHECK_LOGICCELLS
All 478 physical cells in design_cic are missing in logic library.
/home/wtt/test/CIC/pt/lib/smic18 are missing in logic library.
#END_XCHECK_LOGICCELLS
#BEGIN_XCHECK_PHYSICALCELLS
All 2472 logic cells in ff_1v98_0c
ff_1v98_m40c
ss_1v62_125c
tt_1v8_25c
are missing in physical library.
#END_XCHECK_PHYSICALCELLS
4. check library时候的一个error, 我没有看明白是什么意思，请大家指导，谢谢！
#BEGIN_CHECK_PHYSICALPROPERTY
Total number of cells:
0
Information: List of main and reference libraries(LIBCHK-120)
----------------------------------------------------------------------------------
Library namePathUnit tileTile size
----------------------------------------------------------------------------------
design_cic/home/wtt/test/CIC/pt/scriptunit0.660x5.040
smic18/home/wtt/test/CIC/pt/libunit0.660x5.040
----------------------------------------------------------------------------------
List of tile patterns
---------------------------------------------------------------------------------
Tile patternUnit tileLocationOrientationTile size
---------------------------------------------------------------------------------
No tile pattern
---------------------------------------------------------------------------------
Information: List of routing properties(LIBCHK-122)
Unit tile : unitTile
-----------------------------------------------------------------------
PreferredTrack
LayerdirectiondirectionOffsetPitchRemarks
-----------------------------------------------------------------------
METAL1HH0.2800.560OK
METAL2VV0.3300.660OK
METAL3HH0.2800.560OK
METAL4VV0.3300.660OK
METAL5HH0.2800.610offset=0.46pitch
METAL6VV0.3300.950offset=0.35pitch
-----------------------------------------------------------------------
Error: Mismatched and missing data found. Please refer to LIBCHK-122.(LIBCHK-101)
#END_CHECK_PHYSICALPROPERTY
5. check library中的 check tech项遇见很多warning, 也不明白是什么意思，同求指导
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 582) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 582) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 582) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 600) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 618) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 636) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 654) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology data checked and saved in Milkyway log file.
Dumped tech file is design_cic.tf_checker
Logic vs. logic library check summary:
Warning: Library 'ff_1v98_0c(lib#1)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'ff_1v98_0c(lib#1)' is missing CCS receiver models.(LIBCHK-332)
Warning: Library 'ff_1v98_m40c(lib#2)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'ff_1v98_m40c(lib#2)' is missing CCS receiver models.(LIBCHK-332)
Warning: Library 'ss_1v62_125c(lib#3)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'ss_1v62_125c(lib#3)' is missing CCS receiver models.(LIBCHK-332)
Warning: Library 'tt_1v8_25c(lib#4)' is missing CCS driver models.(LIBCHK-332)
Warning: Library 'tt_1v8_25c(lib#4)' is missing CCS receiver models.(LIBCHK-332)
Information: Logic library inconsistencies found for MCMM.(LIBCHK-360)
Information: Logic library inconsistencies found for UPF.(LIBCHK-361)
Information: Logic library inconsistencies found for CCS timing scaling.(LIBCHK-362)
Information: Logic library inconsistencies found for CCS noise scaling.(LIBCHK-362)
Logic library consistency check PASSED for power scaling.
6. 在导入verilog 设计后出现许多undefined module，麻烦大神们给我解释解释吧！
Compiling source file /home/wtt/test/CIC/pt/in/cic_top.v
Warning: Cell 'ADDHX1M.CEL' is created for undefined module 'ADDHX1M'. (MWNL-294)
Warning: Cell 'XOR2X1M.CEL' is created for undefined module 'XOR2X1M'. (MWNL-294)
Warning: Cell 'CLKINVX1M.CEL' is created for undefined module 'CLKINVX1M'. (MWNL-294)
Warning: Cell 'NOR2X1M.CEL' is created for undefined module 'NOR2X1M'. (MWNL-294)
7.导入design后，命令check design,uniquify出现logic cell在physical library 里面不匹配的warning, 然后出现error
Information: linking reference library : /home/wtt/test/CIC/pt/lib/smic18. (PSYN-878)
Warning: The 'XOR2XL' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Warning: The 'XOR2X4' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Warning: The 'XOR2X2' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Warning: The 'XOR2X1' cell in the '/home/wtt/test/CIC/pt/lib/smic18' physical library does not
have corresponding logical cell description. (PSYN-025)
Error: The design is not uniquified. (MWDC-101)
# GUI Debug: Building dc from empty. -- Time: 562ms
Error: Fail to rebuild timing design from database (UID-841)
0
记住一个原则：
physical data要和logic data保持一致性（pin、port）
Error: Mismatched and missing data found. Please refer to LIBCHK-122.(LIBCHK-101)
小编，这个是什么引起的?请指教，谢谢。
受教了，铭记！
学习学习！
Thanks for your share.
是不是需要做maping?
同样是PR新人，求大神出来求证一下。
谢谢分享！