Tie-hi/Tie-low cells for ESD protection

http://www.edaboard.com/thread63856.html
The historical use of Tie-Lo and Tie-Hi cells is almost as much emotional as it is secular.

The reason I say this is that some people use them religiously withoutthought as to why.Depending on your process and your design they mayor may not be necessary. Most people do not know why they are used.

ESD and Reliability are the right answer.In some processes, the gateoxide is very delicate and sensitive relative to the voltage levels ofthe chip.That means for any node with a gate tied to a low impedance,such as a GND or VDD, the voltage on the gate is fixed...but whathappens if the voltage on the drain or source experienced a surge, over ashort period of time, well after enough surges, your oxide reliabilityfails.Generally these surges are fast impulses, either ESD or groundbounce or some other fast transient impules, because if it was DC...thenthe chip would be operating outside the limits of the process.

So how does the tie-lo/Hi work, it works by creating a DC level path buta high impedance AC path on the gate oxide, this allows the voltagelevel on the gate to spike up or down, with voltage surges on its drainand or source, and even though these voltage spikes are capacitivelydivided between all the nodes, because the gate voltage is allowed tofollow or track surges on drains/sources, than the voltage across thedelicate oxides are kept within more tolerant levels than if the gatehad been hard tied to a low impedance GND/PWR.

This is particularly critical on CDM (charge Device Model) ESD type events for IC's.

For almost this exact reason, you see a lot of 65nm and 45nm (even some130 and 90nm) process that do not allow LVT decoupling caps with oxidestied directly to a power or ground terminal (gate leakage problemsaside...though that is also a factor).

They are not always needed and do tend to take up more area.Know yourprocess, your design and the conditions for your design to determine ifyou need them or not...when in doubt however, I would recommend usingthem.

As for how they are designed, there are many formats, the most commonbeing a large resistor in series with the gate, others involving diodesor secondary transistors, etc.

SRFTech

good paper , illustrate the internal machenism of tieoff cells ,
normally tieoff cells insertion is a good practise to protect your ESD ,
it is a must for design under 90nm ,
if not , erc checks will show 'tie to gnd/vdd directly' errors

It seems new

So, the Tie cell is used for ESD and Reliability.

Thank your information.

Thanks very much.
And I have one question about tie cell:
if we have do EDS protection on IO power/ground cells, is it necessary to insert tie cells in core area?

Tt is clear ,ths very much

it's useful