LVS文件的结构解读
#DEFINE metal3_process
//#DEFINE Check_Resistor_WL_Only
#DEFINE Check_Resistor_R_Only
// CSMC 0.50um ST02
// CALIBRE(r) LVS file
// ;;#####################################################################
// ;; (@)# CSMC CALIBRE LVS EXTRACT COMMAND FILE
// ;; (@)# FOR CSMC 0.50UM DPTM 3~5V PROCESS( ST02 )
// ;; (@)# TDR Document: 6S05DPTM-STXX MIXED SIGNAL DESIGN RULE( 9Q04 )
// ;; (@)# METAL LAYER PROCESS: NON-THICK TOP METAL( DPSM/DPDM/DPTM )
// ;;THICK TOP METAL( DPDM/DPTM )
// ;; (@)# DATE: 2010/01/21 (wul)
// ;;#####################################################################
// ;; **********************************************************************
// ;;Environment Setting
// ;;
// ;;1. Process Check Option: Define top metal.
// ;;Such as:
// ;;#DEFINE metaln_process(n=1,2,3)
// ;;OR
// ;;#DEFINE thickmetaln_process(n=2,3)
// ;;
// ;;2. Resistor check option: if only check resistor W/L value, please open
// ;;#DEFINE Check_Resistor_WL_Only( default is ON )
// ;;if only check resistor R value, please open
// ;;#DEFINE Check_Resistor_R_Only( default is OFF )
// ;;
// ;;3. When customer run PEX, if use csmccalibre.xrc.a3 file, this
// ;;calibre.xrc.lvs file should define metal3_process, and if use
// ;;csmccalibre.xrc.t3 file, define thickmetal3_process. and so on.
// ;;
// ;; ***********************************************************************
// ;;########################################################################
// ;;Revision History
// ;;
// ;; Rev.DateWhoWhat
// ;; ----------------------------------------------------------------
// ;;2009.06.02 wangff1.Compare resistor W/L value instead of R value
// ;;2.updata all resistor sheet_resistance
// ;;2009.11.13 wangff1.add each device netlist model name.
// ;;
// ;;2010.01.21 wul1.add check area for BJT devices in LVS command files
//;;#########################################################################
LAYOUT PATH "CELLNEME.gds"
LAYOUT PRIMARY "CELLNAME"
layout system GDS2
SOURCE PATH "CELLNAME.cdl"
SOURCE PRIMARY "CELLNAME"
SOURCE SYSTEM SPICE
MASK SVDB DIRECTORY "svdb" QUERY
PRECISION 1000
RESOLUTION 5
UNIT CAPACITANCE ff
TEXT DEPTH PRIMARY
LVS FILTER UNUSED OPTION YC RE RG AB RC
PORT LAYER TEXT 1001 1003 1005 1020 1022 230
LAYER empty 999
LAYER A1 1000
LAYER MAP 16 DATATYPE 0 1000
LAYER A1_text 1001
LAYER MAP 40 TEXTTYPE 0 1001
TEXT LAYER A1_text
LAYER A2 1002
LAYER MAP 9 DATATYPE 0 1002
LAYER A2_text 1003
TEXT LAYER A2_text
LAYER A3 1004
LAYER MAP 41 DATATYPE 0 1004
LAYER A3_text 1005
TEXT LAYER A3_text
LAYER BA 1006
LAYER MAP 68 DATATYPE 0 1006
LAYER BJT_mark 1007
LAYER MAP 115 DATATYPE 1 1007
LAYER CAP_mark 1008
LAYER MAP 68 DATATYPE 1 1008
LAYER DIODE_mark 1009
LAYER MAP 113 DATATYPE 1 1009
LAYER GT 1010
LAYER MAP 13 DATATYPE 0 1010
LAYER IM 1011
LAYER MAP 93 DATATYPE 0 1011
LAYER ND 1012
LAYER MAP 43 DATATYPE 0 1012
LAYER NS 1013
LAYER MAP 48 DATATYPE 0 1013
LAYER PC 1014
LAYER MAP 14 DATATYPE 0 1014
LAYER PD 1015
LAYER MAP 44 DATATYPE 0 1015
LAYER PS 1016
LAYER MAP 49 DATATYPE 0 1016
LAYER RO 1017
LAYER MAP 23 DATATYPE 0 1017
LAYER SP 1018
LAYER MAP 7 DATATYPE 0 1018
LAYER T2 1019
LAYER MAP 84 DATATYPE 0 1019
LAYER T2_text 1020
TEXT LAYER T2_text
LAYER T3 1021
LAYER MAP 85 DATATYPE 0 1021
LAYER T3_text 1022
TEXT LAYER T3_text
LAYER TB 1023
LAYER MAP 2 DATATYPE 0 1023
LAYER TO 1024
LAYER MAP 3 DATATYPE 0 1024
LAYER W1 1025
LAYER MAP 15 DATATYPE 0 1025
LAYER W2 1026
LAYER MAP 8 DATATYPE 0 1026
LAYER W3 1027
LAYER MAP 140 DATATYPE 0 1027
LAYER RES_HR1K_mark 1028
LAYER MAP 107 DATATYPE 1 1028
LAYER RES_HR2K_mark 1029
LAYER MAP 108 DATATYPE 1 1029
LAYER RES_mark 1030
LAYER MAP 52 DATATYPE 0 1030
LAYER DCTY_mark 1031
LAYER MAP 110 DATATYPE 1 1031
bulk=EXTENT
// A1_lvs=A1 andnot DCTY_mark
A1_lvs=NOT A1 DCTY_mark
// A2_lvs=A2 andnot DCTY_mark
A2_lvs=NOT A2 DCTY_mark
// A3_lvs=A3 andnot DCTY_mark
A3_lvs=NOT A3 DCTY_mark
// BA_lvs=BA andnot DCTY_mark
BA_lvs=NOT BA DCTY_mark
// GT_lvs=GT andnot DCTY_mark
GT_lvs=NOT GT DCTY_mark
// IM_lvs=IM andnot DCTY_mark
IM_lvs=NOT IM DCTY_mark
// ND_lvs=ND andnot DCTY_mark
ND_lvs=NOT ND DCTY_mark
// NS_lvs=NS andnot DCTY_mark
NS_lvs=NOT NS DCTY_mark
// PC_lvs=PC andnot DCTY_mark
PC_lvs=NOT PC DCTY_mark
// PD_lvs=PD andnot DCTY_mark
PD_lvs=NOT PD DCTY_mark
// PS_lvs=PS andnot DCTY_mark
PS_lvs=NOT PS DCTY_mark
// RO_lvs=RO andnot DCTY_mark
RO_lvs=NOT RO DCTY_mark
// SP_lvs=SP andnot DCTY_mark
SP_lvs=NOT SP DCTY_mark
// T2_lvs=T2 andnot DCTY_mark
T2_lvs=NOT T2 DCTY_mark
// T3_lvs=T3 andnot DCTY_mark
T3_lvs=NOT T3 DCTY_mark
// TB_lvs=TB andnot DCTY_mark
TB_lvs=NOT TB DCTY_mark
// TO_lvs=TO andnot DCTY_mark
TO_lvs=NOT TO DCTY_mark
// W1_lvs=W1 andnot DCTY_mark
W1_lvs=NOT W1 DCTY_mark
// W2_lvs=W2 andnot DCTY_mark
W2_lvs=NOT W2 DCTY_mark
// W3_lvs=W3 andnot DCTY_mark
W3_lvs=NOT W3 DCTY_mark
// nbase=BA_lvs and BJT_mark
nbase=AND BA_lvs BJT_mark
// pdiff=TO_lvs and SP_lvs
pdiff=AND SP_lvs TO_lvs
// ndiff=TO_lvs andnot pdiff
ndiff=NOT TO_lvs pdiff
// py2co=W1_lvs and PC_lvs
py2co=AND PC_lvs W1_lvs
// _rhr1k=(PC_lvs interact IM_lvs) and RES_HR1K_mark
L15129=INTERACT PC_lvs IM_lvs
_rhr1k=AND L15129 RES_HR1K_mark
// _rhr2k=(PC_lvs interact IM_lvs) and RES_HR2K_mark
_rhr2k=AND L15129 RES_HR2K_mark
// _rnplus=(ndiff and RES_mark) andnot TB_lvs
L75000=AND RES_mark ndiff
_rnplus=NOT L75000 TB_lvs
// _rnpoly=(GT_lvs andnot SP_lvs) and RES_mark
L28076=NOT GT_lvs SP_lvs
_rnpoly=AND L28076 RES_mark
// _rnwell=TB_lvs and (RES_mark cut TB_lvs)
L15716=CUT RES_mark TB_lvs
_rnwell=AND L15716 TB_lvs
// _rpoly2=(PC_lvs notInteract IM_lvs) and RES_mark
L4614=NOT INTERACT PC_lvs IM_lvs
_rpoly2=AND L4614 RES_mark
// _rpplus=(pdiff and RES_mark) and TB_lvs
L27958=AND RES_mark pdiff
_rpplus=AND L27958 TB_lvs
// _rppoly=(GT_lvs and SP_lvs) and RES_mark
L21689=AND GT_lvs SP_lvs
_rppoly=AND L21689 RES_mark
// baseco=W1_lvs and nbase and pdiff
L93566=AND W1_lvs nbase
baseco=AND L93566 pdiff
// ncoll=TB_lvs and (BJT_mark interact BA_lvs)
L39147=INTERACT BJT_mark BA_lvs
ncoll=AND L39147 TB_lvs
// collco=W1_lvs and ncoll andnot BA_lvs
L50531=AND W1_lvs ncoll
collco=NOT L50531 BA_lvs
// psub=bulk andnot (BJT_mark interact BA_lvs)
psub=NOT bulk L39147
// py1co=W1_lvs andnot PC_lvs and GT_lvs
L61621=NOT W1_lvs PC_lvs
py1co=AND GT_lvs L61621
// nemit=(ndiff and BA_lvs) andnot GT_lvs and BJT_mark
L18939=AND BA_lvs ndiff
L27235=NOT L18939 GT_lvs
nemit=AND BJT_mark L27235
// _qvn10=nemit area==100
_qvn10=AREA nemit ==100
// _qvn20=nemit area==400
_qvn20=AREA nemit ==400
// emitco=W1_lvs and nemit
emitco=AND W1_lvs nemit
// py1con=GT_lvs andnot RES_mark andnot (BJT_mark interact BA_lvs)
L49541=NOT GT_lvs RES_mark
py1con=NOT L49541 L39147
// pgate=(pdiff and py1con) and TB_lvs
L63058=AND pdiff py1con
pgate=AND L63058 TB_lvs
// _mpdep=pgate and PD_lvs
_mpdep=AND PD_lvs pgate
// _mplvt=pgate and PS_lvs
_mplvt=AND PS_lvs pgate
// _mp=(pgate andnot PS_lvs) andnot PD_lvs
L46100=NOT pgate PS_lvs
_mp=NOT L46100 PD_lvs
// ngate=((ndiff and py1con) andnot TB_lvs) andnot RO_lvs
L28496=AND ndiff py1con
L89483=NOT L28496 TB_lvs
ngate=NOT L89483 RO_lvs
// _mndep=ngate and ND_lvs
_mndep=AND ND_lvs ngate
// _mnlvt=ngate and NS_lvs
_mnlvt=AND NS_lvs ngate
// _mn=(ngate andnot ND_lvs) andnot NS_lvs
L99551=NOT ngate ND_lvs
_mn=NOT L99551 NS_lvs
// py2con=((PC_lvs andnot RES_mark) andnot RES_HR1K_mark) andnot RES_HR2K_mark
L80299=NOT PC_lvs RES_mark
L1637=NOT L80299 RES_HR1K_mark
py2con=NOT L1637 RES_HR2K_mark
// _cpip=(py1con and py2con) and CAP_mark
L30710=AND py1con py2con
_cpip=AND CAP_mark L30710
// ndifcon=((ndiff andnot GT_lvs) andnot RES_mark) andnot (BJT_mark interact BA_lvs)
L90206=NOT ndiff GT_lvs
L17171=NOT L90206 RES_mark
ndifcon=NOT L17171 L39147
// ndifco=W1_lvs and ndifcon
ndifco=AND W1_lvs ndifcon
// ntap=ndifcon and TB_lvs
ntap=AND TB_lvs ndifcon
// _dnppw=(ndifcon and DIODE_mark) andnot TB_lvs
L47015=AND DIODE_mark ndifcon
_dnppw=NOT L47015 TB_lvs
// nwelcon=TB_lvs andnot (RES_mark cut TB_lvs) andnot (BJT_mark interact BA_lvs)
L99238=NOT TB_lvs L15716
nwelcon=NOT L99238 L39147
// pdifcon=((pdiff andnot GT_lvs) andnot RES_mark) andnot (BJT_mark interact BA_lvs)
L43580=NOT pdiff GT_lvs
L45818=NOT L43580 RES_mark
pdifcon=NOT L45818 L39147
// pdifco=W1_lvs and pdifcon
pdifco=AND W1_lvs pdifcon
// ptap=pdifcon andnot TB_lvs
ptap=NOT pdifcon TB_lvs
// _dppnw=(pdifcon and DIODE_mark) and TB_lvs
L39653=AND DIODE_mark pdifcon
_dppnw=AND L39653 TB_lvs
// _qvp5=(pdifcon and nwelcon) and BJT_mark area==25
L88314=AND nwelcon pdifcon
L57537=AND BJT_mark L88314
_qvp5=AREA L57537 ==25
// _qvp10=(pdifcon and nwelcon) and BJT_mark area==100
_qvp10=AREA L57537 ==100
// _qvp20=(pdifcon and nwelcon) and BJT_mark area==400
_qvp20=AREA L57537 ==400
#IFDEF metal1_process
CONNECT A1_lvs py1con BY py1co
CONNECT A1_lvs ndifcon BY ndifco
CONNECT A1_lvs pdifcon BY pdifco
CONNECT A1_lvs py2con BY py2co
CONNECT A1_lvs ncoll BY collco
CONNECT A1_lvs nbase BY baseco
CONNECT A1_lvs nemit BY emitco
SCONNECT ndifcon nwelcon BY ntap
LVS SOFTCHK nwelcon CONTACT
SCONNECT pdifcon psub BY ptap
LVS SOFTCHK psub CONTACT
ATTACH A1_text A1_lvs
#ENDIF
#IFDEF metal2_process
CONNECT A2_lvs A1_lvs BY W2_lvs
CONNECT A1_lvs py1con BY py1co
CONNECT A1_lvs ndifcon BY ndifco
CONNECT A1_lvs pdifcon BY pdifco
CONNECT A1_lvs py2con BY py2co
CONNECT A1_lvs ncoll BY collco
CONNECT A1_lvs nbase BY baseco
CONNECT A1_lvs nemit BY emitco
SCONNECT ndifcon nwelcon BY ntap
LVS SOFTCHK nwelcon CONTACT
SCONNECT pdifcon psub BY ptap
LVS SOFTCHK psub CONTACT
LAYER MAP 122 TEXTTYPE 0 1003
ATTACH A2_text A2_lvs
ATTACH A1_text A1_lvs
#ENDIF
#IFDEF metal3_process
CONNECT A3_lvs A2_lvs BY W3_lvs
CONNECT A2_lvs A1_lvs BY W2_lvs
CONNECT A1_lvs py1con BY py1co
CONNECT A1_lvs ndifcon BY ndifco
CONNECT A1_lvs pdifcon BY pdifco
CONNECT A1_lvs py2con BY py2co
CONNECT A1_lvs ncoll BY collco
CONNECT A1_lvs nbase BY baseco
CONNECT A1_lvs nemit BY emitco
SCONNECT ndifcon nwelcon BY ntap
LVS SOFTCHK nwelcon CONTACT
SCONNECT pdifcon psub BY ptap
LVS SOFTCHK psub CONTACT
LAYER MAP 123 TEXTTYPE 0 1005
LAYER MAP 122 TEXTTYPE 0 1003
ATTACH A3_text A3_lvs
ATTACH A2_text A2_lvs
ATTACH A1_text A1_lvs
#ENDIF
#IFDEF thickmetal2_process
CONNECT T2_lvs A1_lvs BY W2_lvs
CONNECT A1_lvs py1con BY py1co
CONNECT A1_lvs ndifcon BY ndifco
CONNECT A1_lvs pdifcon BY pdifco
CONNECT A1_lvs py2con BY py2co
CONNECT A1_lvs ncoll BY collco
CONNECT A1_lvs nbase BY baseco
CONNECT A1_lvs nemit BY emitco
SCONNECT ndifcon nwelcon BY ntap
LVS SOFTCHK nwelcon CONTACT
SCONNECT pdifcon psub BY ptap
LVS SOFTCHK psub CONTACT
LAYER MAP 122 TEXTTYPE 0 1020
ATTACH T2_text T2_lvs
ATTACH A1_text A1_lvs
#ENDIF
#IFDEF thickmetal3_process
CONNECT T3_lvs A2_lvs BY W3_lvs
CONNECT A2_lvs A1_lvs BY W2_lvs
CONNECT A1_lvs py1con BY py1co
CONNECT A1_lvs ndifcon BY ndifco
CONNECT A1_lvs pdifcon BY pdifco
CONNECT A1_lvs py2con BY py2co
CONNECT A1_lvs ncoll BY collco
CONNECT A1_lvs nbase BY baseco
CONNECT A1_lvs nemit BY emitco
SCONNECT ndifcon nwelcon BY ntap
LVS SOFTCHK nwelcon CONTACT
SCONNECT pdifcon psub BY ptap
LVS SOFTCHK psub CONTACT
LAYER MAP 123 TEXTTYPE 0 1022
LAYER MAP 122 TEXTTYPE 0 1003
ATTACH T3_text T3_lvs
ATTACH A2_text A2_lvs
ATTACH A1_text A1_lvs
#ENDIF
nthin = OR _mn ndifcon
DEVICE MN(NN) _mn py1con(G) ndifcon(S) ndifcon(D) psub(B) (S D) <nthin>
NETLIST MODEL "mn"
[PROPERTY w,l,ad,as,pd,ps
width=PERIMETER_COINCIDE(_mn, ndifcon)/2
length=PERIMETER_OUTSIDE(_mn, ndifcon)/2
w=width
l=length
PI_S_OD=perimeter_inside(S,nthin)
IF(PI_S_OD > 0) {
as=area(S)*w/PI_S_OD
ps=perimeter(S)*w/PI_S_OD
} ELSE {as=0 ps=0}
PI_D_OD=perimeter_inside(D,nthin)
IF(PI_D_OD > 0) {
ad=area(D)*w/PI_D_OD
pd=perimeter(D)*w/PI_D_OD
} ELSE {ad=0 pd=0}
]
nlthin = OR _mnlvt ndifcon
DEVICE M(LN) _mnlvt py1con(G) ndifcon(S) ndifcon(D) psub(B) (S D) <nlthin>
NETLIST MODEL "mnlvt"
[PROPERTY w,l,ad,as,pd,ps
width=PERIMETER_COINCIDE(_mnlvt, ndifcon)/2
length=PERIMETER_OUTSIDE(_mnlvt, ndifcon)/2
w=width
l=length
PI_S_OD=perimeter_inside(S,nlthin)
IF(PI_S_OD > 0) {
as=area(S)*w/PI_S_OD
ps=perimeter(S)*w/PI_S_OD
} ELSE {as=0 ps=0}
PI_D_OD=perimeter_inside(D,nlthin)
IF(PI_D_OD > 0) {
ad=area(D)*w/PI_D_OD
pd=perimeter(D)*w/PI_D_OD
} ELSE {ad=0 pd=0}
]
ndthin = OR _mndep ndifcon
DEVICE MD(DN) _mndep py1con(G) ndifcon(S) ndifcon(D) psub(B) (S D) <ndthin>
NETLIST MODEL "mndep"
[PROPERTY w,l,ad,as,pd,ps
width=PERIMETER_COINCIDE(_mndep, ndifcon)/2
length=PERIMETER_OUTSIDE(_mndep, ndifcon)/2
w=width
l=length
PI_S_OD=perimeter_inside(S,ndthin)
IF(PI_S_OD > 0) {
as=area(S)*w/PI_S_OD
ps=perimeter(S)*w/PI_S_OD
} ELSE {as=0 ps=0}
PI_D_OD=perimeter_inside(D,ndthin)
IF(PI_D_OD > 0) {
ad=area(D)*w/PI_D_OD
pd=perimeter(D)*w/PI_D_OD
} ELSE {ad=0 pd=0}
]
pthin = OR _mp pdifcon
DEVICE MN(NP) _mp py1con(G) pdifcon(S) pdifcon(D) nwelcon(B) (S D) <pthin>
NETLIST MODEL "mp"
[PROPERTY w,l,ad,as,pd,ps
width=PERIMETER_COINCIDE(_mp, pdifcon)/2
length=PERIMETER_OUTSIDE(_mp, pdifcon)/2
w=width
l=length
PI_S_OD=perimeter_inside(S,pthin)
IF(PI_S_OD > 0) {
as=area(S)*w/PI_S_OD
ps=perimeter(S)*w/PI_S_OD
} ELSE {as=0 ps=0}
PI_D_OD=perimeter_inside(D,pthin)
IF(PI_D_OD > 0) {
ad=area(D)*w/PI_D_OD
pd=perimeter(D)*w/PI_D_OD
} ELSE {ad=0 pd=0}
]
plthin = OR _mplvt pdifcon
DEVICE M(LP) _mplvt py1con(G) pdifcon(S) pdifcon(D) nwelcon(B) (S D) <plthin>
NETLIST MODEL "mplvt"
[PROPERTY w,l,ad,as,pd,ps
width=PERIMETER_COINCIDE(_mplvt, pdifcon)/2
length=PERIMETER_OUTSIDE(_mplvt, pdifcon)/2
w=width
l=length
PI_S_OD=perimeter_inside(S,plthin)
IF(PI_S_OD > 0) {
as=area(S)*w/PI_S_OD
ps=perimeter(S)*w/PI_S_OD
} ELSE {as=0 ps=0}
PI_D_OD=perimeter_inside(D,plthin)
IF(PI_D_OD > 0) {
ad=area(D)*w/PI_D_OD
pd=perimeter(D)*w/PI_D_OD
} ELSE {ad=0 pd=0}
]
pdthin = OR _mpdep pdifcon
DEVICE MD(DP) _mpdep py1con(G) pdifcon(S) pdifcon(D) nwelcon(B) (S D) <pdthin>
NETLIST MODEL "mpdep"
[PROPERTY w,l,ad,as,pd,ps
width=PERIMETER_COINCIDE(_mpdep, pdifcon)/2
length=PERIMETER_OUTSIDE(_mpdep, pdifcon)/2
w=width
l=length
PI_S_OD=perimeter_inside(S,pdthin)
IF(PI_S_OD > 0) {
as=area(S)*w/PI_S_OD
ps=perimeter(S)*w/PI_S_OD
} ELSE {as=0 ps=0}
PI_D_OD=perimeter_inside(D,pdthin)
IF(PI_D_OD > 0) {
ad=area(D)*w/PI_D_OD
pd=perimeter(D)*w/PI_D_OD
} ELSE {ad=0 pd=0}
]
DEVICE R(RW) _rnwell nwelcon(POS) nwelcon(NEG)
NETLIST MODEL "rnwell"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rnwell, nwelcon)/2
length=PERIMETER_OUTSIDE(_rnwell, nwelcon)/2
r=(length/width) * 821.1
w=width
l=length
]
DEVICE R(RN) _rnplus ndifcon(POS) ndifcon(NEG)
NETLIST MODEL "rnplus"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rnplus, ndifcon)/2
length=PERIMETER_OUTSIDE(_rnplus, ndifcon)/2
r=(length/width) * 65.06
w=width
l=length
]
DEVICE R(RP) _rpplus pdifcon(POS) pdifcon(NEG)
NETLIST MODEL "rpplus"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rpplus, pdifcon)/2
length=PERIMETER_OUTSIDE(_rpplus, pdifcon)/2
r=(length/width) * 168.9
w=width
l=length
]
DEVICE R(NY) _rnpoly py1con(POS) py1con(NEG)
NETLIST MODEL "rnpoly"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rnpoly, py1con)/2
length=PERIMETER_OUTSIDE(_rnpoly, py1con)/2
r=(length/width) * 18.93
w=width
l=length
]
DEVICE R(PY) _rppoly py1con(POS) py1con(NEG)
NETLIST MODEL "rppoly"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rppoly, py1con)/2
length=PERIMETER_OUTSIDE(_rppoly, py1con)/2
r=(length/width) * 18.84
w=width
l=length
]
DEVICE R(RL) _rpoly2 py2con(POS) py2con(NEG)
NETLIST MODEL "rpoly2"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rpoly2, py2con)/2
length=PERIMETER_OUTSIDE(_rpoly2, py2con)/2
r=(length/width) * 53.49
w=width
l=length
]
DEVICE R(H1) _rhr1k py2con(POS) py2con(NEG)
NETLIST MODEL "rhr1k"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rhr1k, py2con)/2
length=PERIMETER_OUTSIDE(_rhr1k, py2con)/2
r=(length/width) * 1077
w=width
l=length
]
DEVICE R(H2) _rhr2k py2con(POS) py2con(NEG)
NETLIST MODEL "rhr2k"
[PROPERTY r,w,l
width=PERIMETER_COINCIDE(_rhr2k, py2con)/2
length=PERIMETER_OUTSIDE(_rhr2k, py2con)/2
r=(length/width) * 1874
w=width
l=length
]
DEVICE C(CP) _cpip py2con(POS) py1con(NEG)
NETLIST MODEL "cpip"
[PROPERTY c
c=AREA(_cpip)*0.00072
]
DEVICE D(ND) _dnppw psub ndifcon
NETLIST MODEL "dnppw"
[PROPERTY A,p
A=AREA(_dnppw)
p=perimeter(_dnppw)
]
DEVICE D(PD) _dppnw pdifcon nwelcon
NETLIST MODEL "dpppw"
[PROPERTY A,p
A=AREA(_dppnw)
p=perimeter(_dppnw)
]
DEVICE Q(P1) _qvp5 psub(C) nwelcon(B) pdifcon(E)
NETLIST MODEL "qvp5"
[PROPERTY A
A=AREA(_qvp5)
]
DEVICE Q(P2) _qvp10 psub(C) nwelcon(B) pdifcon(E)
NETLIST MODEL "qvp10"
[PROPERTY A
A=AREA(_qvp10)
]
DEVICE Q(P3) _qvp20 psub(C) nwelcon(B) pdifcon(E)
NETLIST MODEL "qvp20"
[PROPERTY A
A=AREA(_qvp20)
]
DEVICE Q(N1) _qvn10 ncoll(C) nbase(B) nemit(E)
NETLIST MODEL "qvn10ba"
[PROPERTY A
A=AREA(_qvn10)
]
DEVICE Q(N2) _qvn20 ncoll(C) nbase(B) nemit(E)
NETLIST MODEL "qvn20ba"
[PROPERTY A
A=AREA(_qvn20)
]
TRACE PROPERTY MN(NN) w w 0
TRACE PROPERTY MN(NN) l l 0
TRACE PROPERTY M(LN) w w 0
TRACE PROPERTY M(LN) l l 0
TRACE PROPERTY MD(DN) w w 0
TRACE PROPERTY MD(DN) l l 0
TRACE PROPERTY MN(NP) w w 0
TRACE PROPERTY MN(NP) l l 0
TRACE PROPERTY M(LP) w w 0
TRACE PROPERTY M(LP) l l 0
TRACE PROPERTY MD(DP) w w 0
TRACE PROPERTY MD(DP) l l 0
TRACE PROPERTY C(CP) c c 0
TRACE PROPERTY D(ND) A A 0
TRACE PROPERTY D(PD) A A 0
TRACE PROPERTY Q(P1) A A 0
TRACE PROPERTY Q(P2) A A 0
TRACE PROPERTY Q(P3) A A 0
TRACE PROPERTY Q(N1) A A 0
TRACE PROPERTY Q(N2) A A 0
#IFDEF Check_Resistor_WL_Only
TRACE PROPERTY R(RW) w w 0
TRACE PROPERTY R(RW) l l 0
TRACE PROPERTY R(RN) w w 0
TRACE PROPERTY R(RN) l l 0
TRACE PROPERTY R(RP) w w 0
TRACE PROPERTY R(RP) l l 0
TRACE PROPERTY R(NY) w w 0
TRACE PROPERTY R(NY) l l 0
TRACE PROPERTY R(PY) w w 0
TRACE PROPERTY R(PY) l l 0
TRACE PROPERTY R(RL) w w 0
TRACE PROPERTY R(RL) l l 0
TRACE PROPERTY R(H1) w w 0
TRACE PROPERTY R(H1) l l 0
TRACE PROPERTY R(H2) w w 0
TRACE PROPERTY R(H2) l l 0
#ENDIF
#IFDEF Check_Resistor_R_Only
TRACE PROPERTY R(RW) r r 0
TRACE PROPERTY R(RN) r r 0
TRACE PROPERTY R(RP) r r 0
TRACE PROPERTY R(NY) r r 0
TRACE PROPERTY R(PY) r r 0
TRACE PROPERTY R(RL) r r 0
TRACE PROPERTY R(H1) r r 0
TRACE PROPERTY R(H2) r r 0
#ENDIF
是LVS总是无法通过呢?还是其它问题?能否说详细点?
如果不是要自己写这个commandfile的话，不需要详细了解lvs文件内容的，只需要知道我们应该做哪些修改就行了。另外还要看一下如下部分的attach定义，根据这些定义确定你如何在版图上打pin
ATTACH A3_text A3_lvs
ATTACH A2_text A2_lvs
ATTACH A1_text A1_lvs
弄明白runset的话 其实很麻烦 ，建议还是去专门的培训课程吧。
看懂没有很难吧，要沉下心去看，语法上其实很简单。
弄明白runset的话 其实很麻烦 ，建议还是去专门的培训课程吧。
同意這個看法
DCTY mark干嘛用的?
貌似是unlvs层
百度文库上面有中文的教程，还算简单明了。要真正弄清楚的话，还是得花点时间的。
学习了
了解了解
不知道小编是否学会看懂LVS文件，可不可以指导一二。
看懂很容易啊，沉下心慢慢看，有不懂的语法去查svrf guide
涨涨人气
LVS主要的结构就是先给层次命名，比如 LAYOUT A1 1001。命名完就是器件的构成如rpoly2=AND L1146 RES_mark就是说poly和电阻标识层一起构成一个poly电阻。
学习了