请教一个clock gating影响scan coverage的问题
1. 综合的时候加了-gate_clock之后coverage比不加低了2个百分点
工具加的clock gating 的TE端可以正确的接到scan enable上面
比较了两次的log，多出来的一些violation是这样的：
512 Level sensitive port captured data affected by new capture violations (C5)
540 Level sensitive port clock path affected by new capture violations (C8)
C5的其中一个是这么说的
Warning: Clock SCANCLK can capture new data on LS input CK of DFF ../latch. (C5-188)
C8是这样的
Warning: SCANCLK clock path affected by new capture on LS input CK of DFF .../latch. (C8-420)
这个latch就是工具加的 clock gating，
个人做前端经验比较多，DFT第一次做，请问这个clock gating应该怎么提高coverage呢?
2. 另外请教一个问题，前段为了做一些IP的clock控制，在rtl里加入了一些clock gating，TE端接到了scan mode上面，这个在scan的shift和capture阶段都是一直有效的，violation里面曝出了这些clock gating的逻辑就测不全了，请问这些是不是就没办法测到了。
非常感谢！
2 gating 逻辑到IP外面和别的信号与或一下用scan_md 做mux出来，要不然是不是信号就断在black box里面了
查一下出来的网表里面clock gate上的TE信号连得是scan enable还是test mode/scan mode，如果是test mode/scan mode必然会导致cov下降
把手动例化的clock gate 用mux 和test mode 信号bypass掉。这样覆盖率是可以上来。
但这应该不是最好的做法
是scan en，这个是tool插的，
只有手动例化的clk gate TE端我接死到了scan mode
不是吧，只不过在scan mode下面这个clock gate的逻辑因为TE 是constant就有些功能测不到了
导致coverage下降
就是这个意思啊，产生gaten 信号的逻辑就测不到了，虽然你scan_md会使得clk常开，
那可以破吗，我可以把SCAN enable接上去，不过怎么让tool知道呢？
诸位，这个问题基本上解决了，
1,实际上是我在做clock结构的时候，有一个地方没有让scan clk在scan mode下直通过去导致了tool自己加了很多clock mux在gate前面来bypass scan clock
2. scan en 连到手动instance的gate上貌似没有报什么violation，coverage也有提高，不过还要仿真验证一下。
谢谢各位了，不过coverage还是不行，我要在自己研究研究呢
现在爆出来还有一个clock相关的violation是：
Warning: Clock SCANCLK can capture new data on TE input CKN of DFF .../rptr_reg_4_. (C6-1)
Source of violation: input CK of DFF ..../u_spi_sfifo_tx/rempty_reg.
这其实是一个用负沿的寄存器，请教如何处理这个问题，tool对于C6这个violation的解释
C6
NAME
C6 Clock C can capture new data on TE input I1 of <type> S1. Source of
violations: input I2 of <type> S2.
Default Severity: Warning
DESCRIPTION
A clock must not capture data into a trailing edge (TE) input if that
data can be affected by new captured data. C is the clock port; the
<type> is either DLAT (latch) or DFF (flip-flop); I1 and I2 are input
pin names; S1 and S2 are cell names.
Violation of this rule has the following effects:
* Introduces the risk that test generation might need an additional simulation pass and will not correctly control the new value that is captured, resulting in some loss of test coverage.
* A potential rule violation occurs on a clock if a clock input of a TE pin is in the clock cone and its data input (including RAM address) is in the effect cone. This input is called the sink of the violation. To be considered a violation, the source must not be a TE pin, the source clock must be capable of being at 1 (0 if LE) when the sink clock is at 1, and it must be possible to propagate the path from source to sink under this condition.
A clock cone is the cone of combinational logic fanning out from a sin-
gle clock input port and extending to one or more sequential device
input pins or a primary output port. An effect cone is the cone of com-
binational logic fanning out from the output pin of a sequential device
(clocked by CLK1 for example) and extending through all combinational
logic until it reaches other sequential devices or primary output
ports. An effect cone is always relative to a specific clock (CLK1)
connected to the clock/set/reset pin of a sequential device.