有人做过电源管理芯片的HTOL吗

不加负载，大电流应用的可靠性怎么保证?比如rdl layer的电子迁移?

理论来说htol只是加速test的一种方法，剔除早期失效，保证10年稳定工作还是10年全负荷工作是你们自己考虑的事。  
  记得有个JESD标准

我看htol只是为了保证芯片内部的结在高温高压下的可靠性，通常都没提到大电流的问题，那全负载工作的长期可靠性该用什么老化测试保证?

HTOL并不只是为了看高温下的可靠性，高温是用来加速老化的手段

对...高温高压只是加速老化....
可是如何把HTOL和大电流工作的可靠性联系起来呢?

wiki上面关于htol的解释,好像也是建议加上负载的...
Analog modules operation
The recent trend of integrating as many electronic components as possible into a single chip is known as system on a chip (SoC).
This trend complicates reliability engineers' work because (usually) the analog portion of the chip dissipates higher power relative to the other IC elements.
This higher power may generate hot spots and areas of accelerated aging. Reliability engineers must understand the power distribution on the chip and align the aging so that it is similar for all elements of an IC.
In our hypothetical SoC the analog module only includes a voltage regulator. In reality, there may be additional analog modules e.g. PMIC, oscillators, or charge pumps. To perform efficient stress tests on the analog elements, reliability engineers must identify the worst-case scenario for the relevant analog blocks in the IC.For example, the worst-case scenario for voltage regulators may be the maximum regulation voltage and maximum load current; for charge pumps it may be the minimum supply voltage and maximum load current.
Good engineering practice calls for the use of external loads (external R,L,C) to force the necessary currents. This practice avoids loading differences due to the chip's different operational schemes and operation trimming of its analog parts.

带载，有结温要求，>125度即可。
Jedec，认可output open。