Re: ECO DFF Clock Gating问题

Yes, you can do that if you just want to insert a single DFF. but the question is, you should check the clock skew between the new DFF and other sinks (under the clock tree with ICG) and try to do STA under all corners to make sure there is no setup/hold violation.
To realize this target, you should check the new DFF clock latency and compare to the CTS latency under that clock domain and try to make it locate at the leaf side of the clock tree. Please ignore this comment if your ECO has special purpose.
Be careful if this new DFF is used to generate some ENABLE for other ICGs.

another comment, after the DFF is inserted, check the clock point transition time carefully. Usually, clock net transition time has a stricter rule that normal data net. And, you should avoid new cross-talk effect caused by the new clock net.
Good Luck.

STA and formal will take care of any potential timing/SI/functional problems.
All sign-off checks should be kicked off after any simple ECO