请教问题——用Verilog-A实现的十位计数器

module counter_5(B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, CLK);
electrical     B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, CLK;
parameter real trise = 0.1p;
parameter real tfall = 0.1p;
parameter real tdely = 0.1p;
parameter real vlogic_high = 3.3;
parameter real vlogic_low  = 0;
parameter real vtrans_clk  = 1.6;
`define num_bits  10
integer i;
integer m;
integer halfscal;
real fun[0:`num_bits-1];
analog begin
  @ (initial_step)
   i=349;

  @ (cross(V(CLK) - vtrans_clk, 1)) begin
   halfscal = 512;
  
    if (i==1023)
    i=0;
    
    else
    i=i+1;
  for (m=9; m>=0; m=m-1)
  begin
   if (i > halfscal-1)
   begin
   fun[m]=vlogic_low;
   i = i - halfscal - 1;
   halfscal = halfscal / 2;
   end
   else
   begin
   fun[m]=vlogic_high;
   halfscal = halfscal / 2;
   end
   end
end
V(B9) <+ transition( fun[9], tdely, trise, tfall );
V(B8) <+ transition( fun[8], tdely, trise, tfall );
V(B7) <+ transition( fun[7], tdely, trise, tfall );
V(B6) <+ transition( fun[6], tdely, trise, tfall );
V(B5) <+ transition( fun[5], tdely, trise, tfall );
V(B4) <+ transition( fun[4], tdely, trise, tfall );
V(B3) <+ transition( fun[3], tdely, trise, tfall );
V(B2) <+ transition( fun[2], tdely, trise, tfall );
V(B1) <+ transition( fun[1], tdely, trise, tfall );
V(B0) <+ transition( fun[0], tdely, trise, tfall );
`undef num_bits
end
总是出问题，想问下版上这个方面的高手，问题出在哪里？谢谢各位了

就贴断代码上来...也没个问题说明..
code review很花时间的

中午居然看了一眼
endmodule估计是你粘贴时候漏掉了
initial step时候fun[0-9] 没有定义，会有Op问题