猎头职位，30万左右年薪： PR 和 PV各一个
时间：12-12
整理：3721RD
点击：
作为水木老站友，作为IC老民工，我专为IC“民工”谋福利。
自己有兴趣的自己看，自己没兴趣多宣传，多谢了各位。
YestinAi@gmail.com
工作地：上海
Staff Physical Design Engineer 2
Responsibilities:
Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Define and evolve backend low-power design methodology in 40nm technology to support aggressive low-power techniques for chips having multiple power-domains and dynamic voltage-scaling.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Integrate of analog and RF-macros using their library models and closing timing at the interface level.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule,resource requirements and track backend schedule.
Qualifications:
Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.
Proven track records of leading multiple product tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.
Vast experience identifying and resolving physical implementation issues related to Congestion, Routing & Timing Closure (including Crosstalk)
Hands on experience and detailed knowledge of Synopsys (preferred), Cadence or Magma Physical Design-tools.
Expertise in scripting languages like PERL, TCL, AWK, shell, etc. Must be a team player with excellent verbal and written communication skill.
8+ years of direct experience on physical design (MS 6+ years)
PV类似
自己有兴趣的自己看，自己没兴趣多宣传，多谢了各位。
YestinAi@gmail.com
工作地：上海
Staff Physical Design Engineer 2
Responsibilities:
Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Define and evolve backend low-power design methodology in 40nm technology to support aggressive low-power techniques for chips having multiple power-domains and dynamic voltage-scaling.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Integrate of analog and RF-macros using their library models and closing timing at the interface level.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule,resource requirements and track backend schedule.
Qualifications:
Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.
Proven track records of leading multiple product tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.
Vast experience identifying and resolving physical implementation issues related to Congestion, Routing & Timing Closure (including Crosstalk)
Hands on experience and detailed knowledge of Synopsys (preferred), Cadence or Magma Physical Design-tools.
Expertise in scripting languages like PERL, TCL, AWK, shell, etc. Must be a team player with excellent verbal and written communication skill.
8+ years of direct experience on physical design (MS 6+ years)
PV类似