KT猎头代招-physical design leader
时间：12-12
整理：3721RD
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英国design service公司招physical design leader，工作地点在上海，技术业内领先，有兴趣的朋友请和我联系：
Mail:raymond-chen@kthr.com
MSN: utopia.chen@hotmail.com
Job Description
we are looking for motivated engineers who can show they are capable of learning to work on complex IC designs, to the highest quality and in record time. our engineers have expertise in delivering the lowest power solutions in advanced technologies, covering technologies down to 28nm, design sizes in excess of 300mm2, and applications from mobiles, to graphics and network IC's. We work with leading EDA and IP companies, and its expertise has been recognised through its alliance partnerships with SMIC and TSMC.
Depending on experience, key responsibilities will involve some of the following:
Development and optimisation of high performance and low power Soc physical implementation methodology
Working with European engineers to do block level and full chip floor planning, timing and power analysis, and P&R
Design consulting in customer's offices on physical implementation tasks
Interfacing with foundry and IP providers on IP imports and test definition.
Desired Skills and Experience
Some experience in physical design engineering coupled with a good degree and a desire to be at the leading edge of new technologies.
The successful applicants will have exposure to at least some of the following areas:
· Digital Soc chip design and implementation
· Design automation and analysis using scripting languages, particular Tcl and Perl
· Design Flows and the EDA tools, in particular tools from Magma, Mentor and Synopsys. Experience with tools from Apache and Azuro would be an advantage
· Sign-off methodology and EDA tools for STA, Noise, Power, etc.
· Structured design styles involving placed gates
· ATPG tools and methodologies.
Mail:raymond-chen@kthr.com
MSN: utopia.chen@hotmail.com
Job Description
we are looking for motivated engineers who can show they are capable of learning to work on complex IC designs, to the highest quality and in record time. our engineers have expertise in delivering the lowest power solutions in advanced technologies, covering technologies down to 28nm, design sizes in excess of 300mm2, and applications from mobiles, to graphics and network IC's. We work with leading EDA and IP companies, and its expertise has been recognised through its alliance partnerships with SMIC and TSMC.
Depending on experience, key responsibilities will involve some of the following:
Development and optimisation of high performance and low power Soc physical implementation methodology
Working with European engineers to do block level and full chip floor planning, timing and power analysis, and P&R
Design consulting in customer's offices on physical implementation tasks
Interfacing with foundry and IP providers on IP imports and test definition.
Desired Skills and Experience
Some experience in physical design engineering coupled with a good degree and a desire to be at the leading edge of new technologies.
The successful applicants will have exposure to at least some of the following areas:
· Digital Soc chip design and implementation
· Design automation and analysis using scripting languages, particular Tcl and Perl
· Design Flows and the EDA tools, in particular tools from Magma, Mentor and Synopsys. Experience with tools from Apache and Azuro would be an advantage
· Sign-off methodology and EDA tools for STA, Noise, Power, etc.
· Structured design styles involving placed gates
· ATPG tools and methodologies.