问个DC synthesis的问题

帮你copy 一个过来：
Question:
I am using Design Compiler version Z-2007.03.  Is there a way to NOT
'uniquify' a design during synthesis? By the way, we don't want to do
bottom-up synthesis and apply set_dont_touch on modules. Is there a simpler
way to turn off 'uniquify'?
Answer:
We are not aware of any method besides applying set_dont_touch to prevent
compile or compile_ultra from uniquifying multiply-instantiated modules.
Automatic multiple instance management (by using uniquify) became part of
the
compile flow from version 2004.06. It used to be a separate step.
Uniquify was being run on the majority of all designs and it could be
problematic if the step was omitted. The benefit is improved quality of
results (QoR) by ensuring that each multiply-instantiated design is
optimized
within its environmental context. For more information, see the section on
Resolving Multiple Instances of a Design in Design Compiler User's Guide at
the following links:
https://solvnet.synopsys.com/dow_retrieve/Z-2007.03/dcrmo/dcrmo_2.html
https://solvnet.synopsys.com/dow_retrieve/Z-2007.03/dcug/dcug_9.html
The compile command does not have a -no_uniquify option.  The compile_ultra
command is actually a high-performance encapsulated flow that performs a
full DC-Ultra compile, followed by an incremental compile. The -no_uniquify
option in compile_ultra only applies to the initial compile, in order to
save
runtime, while the subsequent incremental compile still automatically
uniquifies the design.
In short, there is only one method to prevent the automated uniquify
from affecting particular designs and that is by using the
set_dont_touch command.