微波EDA网,见证研发工程师的成长! 2025婵犵數濮烽弫鍛婃叏閹绢喗鍎夊鑸靛姇缁狙囧箹鐎涙ɑ灏ù婊呭亾娣囧﹪濡堕崟顓炲闂佸憡鐟ョ换姗€寮婚敐澶婄闁挎繂妫Λ鍕磼閻愵剙鍔ゆ繛纭风節瀵鎮㈤崨濠勭Ф闂佸憡鎸嗛崨顔筋啅缂傚倸鍊烽懗鑸靛垔椤撱垹鍨傞柛顐f礀閽冪喖鏌曟繛鐐珕闁稿妫濋弻娑氫沪閸撗€妲堝銈呴獜閹凤拷04闂傚倸鍊搁崐鎼佸磹閹间礁纾归柟闂寸绾剧懓顪冪€n亝鎹i柣顓炴閵嗘帒顫濋敐鍛婵°倗濮烽崑鐐烘偋閻樻眹鈧線寮撮姀鈩冩珕闂佽姤锚椤︻喚绱旈弴銏♀拻濞达綀娅g敮娑㈡煕閺冣偓濞茬喖鐛弽顓ф晝闁靛牆娲g粭澶婎渻閵堝棛澧遍柛瀣仱閹繝濡烽埡鍌滃幗闂佸搫娲ㄩ崑娑㈠焵椤掆偓濠€閬嶅焵椤掍胶鍟查柟鍑ゆ嫹23闂傚倸鍊搁崐鎼佸磹閹间礁纾归柟闂寸绾剧懓顪冪€n亝鎹i柣顓炴閵嗘帒顫濋敐鍛婵°倗濮烽崑鐐烘偋閻樻眹鈧線寮撮姀鈩冩珖闂侀€炲苯澧扮紒顕嗙到铻栧ù锝堟椤旀洟姊洪悷鎵憼闁荤喆鍎甸幃姗€鍩¢崘顏嗭紲闂佺粯鐟㈤崑鎾绘煕閵娿儳鍩g€殿喖顭锋俊鎼佸煛閸屾矮绨介梻浣呵归張顒傜矙閹达富鏁傞柨鐕傛嫹 闂傚倸鍊搁崐鎼佸磹閹间礁纾归柟闂寸绾剧懓顪冪€n亝鎹i柣顓炴閵嗘帒顫濋敐鍛婵°倗濮烽崑鐐烘偋閻樻眹鈧線寮撮姀鐘栄囨煕鐏炲墽鐓瑙勬礀閳规垿顢欑紒鎾剁窗闂佸憡顭嗛崘锝嗙€洪悗骞垮劚濞茬娀宕戦幘鑸靛枂闁告洦鍓涢敍娑㈡⒑閸涘⿴娈曞┑鐐诧躬閹即顢氶埀顒€鐣烽崼鏇ㄦ晢濠㈣泛顑嗗▍灞解攽閻樺灚鏆╁┑顔芥尦楠炲﹥寰勯幇顒傦紱闂佽宕橀褔鏌ㄩ妶鍡曠箚闁靛牆瀚崗宀勬煕濞嗗繑顥㈡慨濠呮缁辨帒螣閼姐値妲梻浣呵归敃銈咃耿闁秴鐒垫い鎺嶈兌閸熸煡鏌熼崙銈嗗濠电姷鏁告慨鐑藉极閸涘﹥鍙忛柣鎴f閺嬩線鏌熼梻瀵割槮缁炬儳顭烽弻锝夊箛椤掍焦鍎撻梺鎼炲妼閸婂潡寮诲☉銏╂晝闁挎繂妫涢ˇ銉х磽娴e搫鞋妞ゎ偄顦垫俊鐢稿礋椤栨氨鐤€闂佸憡鎸烽懗鍫曞汲閻樼數纾藉ù锝呮惈椤庡矂鏌涢妸銉у煟鐎殿喖顭锋俊鎼佸煛閸屾矮绨介梻浣呵归張顒傜矙閹达富鏁傞柨鐕傛嫹
首页 > 硬件设计 > 硬件工程师文库 > 数据链路层发送与接收的处理过程及涉及到的模块

数据链路层发送与接收的处理过程及涉及到的模块

时间:02-08 来源:网络整理 点击:

ter per frame cycle

1 ... 32

S<4:0>

Binary value minus 1

SCR

Scrambling enabled

0 ... 1

SCR<0>

Binary value

SUBCLASSV

Device Subclass Version 000 – Subclass 0 001 – Subclass 1 010 – Subclass 2

0 … 7

SUBCLASSV

<2:0>

Binary Value

RES1

Reserved field 1

0 ... 255

RES1<7:0>

Binary value

RES2

Reserved field 2

0 ... 255

RES2<7:0>

Binary value

CHKSUM

Checksum Σ(all above fields)mod 256

0 ... 255

FCHK<7:0>

Binary value

*?CF==L?shall always be encoded as 31: control words on all lanes.?CF==31 can only occur when?L==31, see 5.1.3.

Configuration octet no.

Bits

MSB

6

5

4

3

2

1

LSB

0

DID<7:0>

1

ADJCNT<3:0>

BID<3:0>

2

X

ADJDIR<0>

PHADJ<0>

LID<4:0>

3

SCR<0>

X

X

L<4:0>

4

F<7:0>

5

X

X

X

K<4:0>

6

M<7:0>

7

CS<1:0>

X

N<4:0>

8

SUBCLASSV<2:0>

N’<4:0>

9

JESDV<2:0>

S<4:0>

10

HD<0>

X

X

CF<4:0>

11

RES1<7:0> - Set to all X

12

RES2<7:0> - Set to all X

13

FCHK<7:0>

1.4.3 Lane alignment buffering /detection and monitoring

在开始数据帧和通道对齐后,通道将会进入对齐字节检测状态,通道的对齐是通过对齐标志符/A/=/28.3/来决定的,该对齐标志符在复帧的结尾,对于对齐标识符A的插入,可以参考frame alignmentmonitoring。

在一般的情况下,不是所有的通道都会发生同时发生对齐标识符A,但是通道可以通过A在复帧中的位置来检测数据通道的数据是否同步上。

在多个接收通道的情况下,每一个接收器都应该可以从更高层的应用中授权数据链路层对链路中的数据进行从新的动态调整,已完成不同数据通道间的对齐。

 数据通道中发现未对齐

 发现新的对齐字符,但是不在数据复帧的帧尾

 根据对齐字符缓存区中的数据进行从新对齐

 如果连续接在同一个位置上接收到两个有效的A,并且不在数据复帧的结束,并且在两个A之间没有接收到有效或者无效A标识符,通道需要从新的将通道中的数据进行对齐。

 如果在最近的数据帧出现通道间不对齐的可能性很大时,接收器需要将第一个接收到A的位置作为对齐的标准。

1.4.4 Lane alignment detection andmonitoring

通道间的数据检测和对齐处理过程如图27所示,图中变量的具体意思参照表8,具体的操作流程如下:

Variable

Meaning

A_received

Asserted when the current symbol, before possible substitution in frame alignment monitoring, corresponds to control character K28.3

CROSS_COUPLING

Lane misalignment expected because of cross coupling between frame and lane alignment

Fcounter

Counter used to mark the position of the current frame in the multiframe. Frame indexing starts from 0.

K

Number of frames in multiframe.

previous_A_position

Variable into which to store the position in the multiframe of a K28.3 symbol

REPLACE_A

Replace the K28.3 at the decoder output by:

? The data character decoded or used at the same position in the previous frame when scrambling is disabled

? D28.3 when scrambling is enabled

?

However, if the position of the K28.3 is required in subsequent frame alignment monitoring, the K28.3 shall not be replaced or it shall be marked.

RESET_FRAME_COUNTER

Reset frame counter to zero at reception of next frame

INITIATE_SYNC_CHECK

In receivers belonging to a MCDA device class (see clause 9), if authorized via the control interface, initiate a synchronization check between the LMFCs via one of the methods supported by the device class and subclass.

VALID

灏勯涓撲笟鍩硅鏁欑▼鎺ㄨ崘

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top