settling time of synthesizer

Would someone tell me
what's the relation among the settling time of synthesizer, carrier frequency and signal bandwith.

It depend on the synthesizer. Generally it uses PLL methods and so the time to change frequency is in round numbers 2 or 3 times the inverse of the PLL loop bandwidth.

For DDS type generators it is much less than one sine wave cycle time.

Tset=(2.5~3)/BW, BW is the bandwidth of PLL.