how to simulate settling time of a PLL circuit [hlp]
how we can analyze and simulate settling time and time responce of a PLL? which software help us?
Principle of simulation:
In most cases it is useful to simulate a certain parameter based on its definition. This applies also to the present case. Therefore, make several simulations in the time domain to find an incoming frequency which enables lock within one period of the beat frequency. Then, you simply can read the time until lock has occured.
Simulation programs: If you want to simulate on parts level you can use any of the known software packages - mostly based on the SPICE kernel.
I personally prefer simulation on a block system level. In this context, I like VISSIM as it is easy to use and powerful (VISSIM.com).
to know the settling time plot the control voltage while simulating in time domain and see at what time it stabilises.