Settling time specification

Hi,
I'm designing an RF frequency synthesizer (sigma-delta fractional-N PLL) for an LTE sys. , in system level design, I need the synthesizer specifications , how can I determine the Settling Time spec ? ... I can't find any condition in LTE standard on how fast can the system changes the channel ... How can I determine this spec ??

The settling time in frequency synthesizers is specified as the time delay between the command end and the frequency stabilized at the commanded value.
Some synthesizers typically settle within a fraction of a second, special "fast-settling" types, within < one millisecond.

Start with the channel handoff timing requirements and go from there.

Dave

You can use ADISimPLL to simulate and get comparable setting time to lock a VCO.