Problem with settling time of a PLL
I am designing a pll now. When I do the tran simulation of the pll, a problem encoutered. We can get from the paper or book that the pll settling time is about 3/bandwidth. However, at startup of the pll, the phase between the vco and ref is unknown, there will be a problem when fref>fvco, meanwhile the phase of the ref lag the vco.That is because, idealy, fref>fvco, cp should be charging to increase the frequency of vco, but at the start, the phase of vco leads the ref and so cp has to discharge until the ref leads the vco. My question is that how can we avoid this problem? Or, if we cannot avoid this problem, how can we estimate this time or decrease this time?
Thanks
At the input of the PFD, simply swap ref signal and the feedback signal.
I am not sure if I undertand your problem, but it sounds like you want the integrator capacitor to approach the correct locked frequency from one particular direction. If that is true, you can precharge the capacitor to the desired start point (thru some high impedance resistors), and then let the PLL eventually over-ride it.
Thanks for the reply.
AdvaRes`s suggestion is simply swapping ref signal and the feedback signal, however at the start of the pll, we do not know what is the situation. Maybe we need not swap the two signal or we need swap the two signal. If we use this suggetion, how can we make sure that we need do this?
Biff44, absolutely that you have got my problem. However, your suggestion can solve the frequency difference, but my problem is how to solve the phase difference? How can I make the integrator capacitor to approach the correct locked frequency from the right direction?
Actually, you can know the situation. At initial conditions, at the moment when you power the PLL VCO control voltage is near the zero. Suppose that your VCO characheristic is a decreasing line. When Vtune is near zero the VCO frequency is much more big than the reference frequency. If you you use the feedback signal to discharge the filter's capa its voltage will converge to zero coz of the the high feedback frequency. Thus the Feedback signal has to be used to charge the capa.
Similarly, if the VCO curve is an increasing line than the feedback is used to discharge.
Thanks tor AdvaRes`s reply.
However, it seems that you have not got my problem. My problem is that: at the start, as from frequency difference, pll should charge or discharge, but as from phase difference, pll has to discharge or charge. These two situtaiton is opposite. What
Added after 3 minutes:
Additionly, when pll powers on, pll will enter into AFC mode first, and then enter into normal settling time. Therefore, the intial voltage input to vco, is about vdd/2.
Ok I see. It's like you set VCO Vtune at initial condition.
You can resolve your problem by playing on the value of the Bandwidth/phase margin of your PLL.
In the old days, back when Hector was still a pup, we actually swept the vco tuning voltage with a sawtooth ramp. That way you were guaranteed that the vco frequency would eventually tune its way inside of your capture range of the PLL, and insure lockup. The PLL gain constants were such that the ramping input (just a fixed DC current to the integrator) would be overcome by the phase detector when actual lock was established.
First I should thanks for your reply, AdvaRes and biff44.
I have got AdvaRes`s suggestion, you think that the initial frequency difference is small, so the small signal model can work here. But if I cannot use a big Icp and what`s worse, the bandwidth is small than 50 khz, because of 500KHz reference. And meantime, I should make the settling time below about 120u. How can I promise this time?
From biff44`s reply, I get that pll settling time includes two parts, the first is large signal whose time depends on Icp, and the last is small signal whose time depends on pll bandwidth and phase marging. And my problem is that if I want to reach a quick settling time as soon as possible, bases on 50KHz bandwidth and 100uA Icp (which are the maximum), what can I do?
Thanks,