[help] LNA, Mixer bias circuit.

The NPN transistor model is characterized by single transistor. When connecting n NPNs in parallel to consiste a current mirror, the model does not take account of the interconnect parasitic effect. I think, before we do the parasitic extraction from layout, the larger number of n, the less accurate model we get. That will greatly affect the simulation accuracy if this structure is used in the LNA or mixer input. I am wondering how people handle this problem. Thanks.

Hi,
1-don't worry about the parasitics in bias section of the circuit especially for the the base line of transistors.
2-you can increase the the number of transistor in the ref side.
3-you can increase the refrence current.

Regards

You mean the base line has less parasitic effect due to the small base current?
I do not worry about the DC characteristic of the current mirror. My concern is the RF performance. If that is the LNA input, which is very sensitive to the model accuracy, will this have large effect on the LNA performance?

I meant why are you worry about the parasitics in the bias section of an RF circuit(current source section)?

you must be worry about the parasitics in high frequency path from input to output.

Have you used the current mirror in RF path?
what is your RF circuit?
Regards

If the parasitics you mentioned are L & C, then they could be ignore when you calculatre the DC operation point. Because DC means freq.=0Hz.

The parasitics you care should be the line resistance.

i believe whether taking parasitics into account just depends on ur frequence and ur size