[LNA] What's wrong with its gain?
The LNA is using the traditional single end cascode structure with source degeneration inductior.
Is there something wrong with the LNA?Thanks.
The waveform looks quite unusual, there MIGHT be something wrong.
The above simulation result is using the Gummel Poon model. I use the HICUM model of the same device from the same foundry and get the following result:
This curve is reasonable
In the first curve, I suppose that there is a feedback mechanism that tries to create an instability.Or phase margin is as low and the circuit is near to oscillate.. But it's very dangerous.
The second is quite well
First of all, these two graphs are results from the same LNA which is using SiGe. The different is the npn bjt of the first one is using Gummel Poon model while the 2nd one is using HICUM model (I can switch between these two models by simply changing an option). The 2nd one is quite reasonable though still has some strange performance.
Second, S12 of both simulation are less than -40db. The stablility tests are shown here:
I have checked all the MU numbers, they are all not less than 1, but most of them are equal to 1, which I think is too close to the boundary, but that should be cause by the matching network. Because before adding any i/o matching network, the stability plot is like below pic, which means the matching network degrade the stability. Anyone can suggest how to avoide this degradation? The LNA schematic is shown in the last pic.
A stability factor around unity with simulated S12 <-40 is very very dangerous.
The problem is in the model of the transistor, of course. There is a simulator problem, I think. Have you tried to make simulations with very strict accuracy settings? Are you using direct HB or Krylov?
Try to avoid the sweep in HB and verify in a single point simulation the gain of the circuit at critical input power. The HB simulator
Also, try to use real components models (at least with Q). This is more realistic in term of expected performances, and usually helps the simulator in reaching good convergenses.
I hope it can help.
Mazz
Can you elaborate on this? Thanks !
Because S12 would be much greater after you mount you chip onto PCB. It is very hard to keep S12 <-40 at GHz range.
I think the key point is not a small S12. What we expect from the simulation result is a S12 as small as possible, though, as you said, it will be degrade significantly in the real world. The important things are:
1. Up to what frequency should we ensure the circuit stable? (normally I give a freq value 10 times as the operation freq)
2. As my case, all numbers of stability factor (MU) are not less than 1. Theoretically this circuit is unconditionally stable. However, we do worry about the real product will become unstable due to the too small stability margin. So the question is how much MU margin should we provide?
3. According to the book "Practical RF Circuit Design for Modern Wireless Systems Vol. 2 - Active Circuits and Systems" Page 58, the author says "...At those frequencies, the μ-factor is closer to unity value. Still, considering that matching circuit losses will most likely improve stability, we do not have to worry about oscillation." Do you agree with that?
My LNA operates at 1.6GHz, is the following stability plot ok? I have tried to increase the MU number but can not figure out how to do that. The LNA is using the true model provided by foundary. Only the i/o matching networks use ideal LC component. Before matching the circuit is unconditional stable with quite enough margin (as shown in the above graphs). However after adding the matching network, MU shows a peak at 1.6GHz and drop dramatically to very close to 1 at other frequency even though the S12 remains less than -40db. Why?
Agree
Default setting, HB simulation, Direct Solver.
What other simulation can do this job?
Only i/o matching networks use ideal LC components. I don"t think the weird result is casued by these ideal LCs.
The other simulator is Spectre RF, but I didn't mean it.
I mean try to simulate with HB only a single point, for example Pin=-22 dBm, where you see the difference.
In non-linear analysis is always a good practice and is always recommended to use strict convergence settings. for this simple circuit this will not increase too much simulation time.
Using real LC, you can verify by yourself that real matching circuit losses increase stability.
I think that you're at a good starting point of your design! The bias can be a long design...then go to layout and tune it: the hard job is still at the beginning.
I hope it can help.
Mazz
If I were a betting man, I would bet that as the Pout increases, the device's output impedance changes, and the output impedance match gets better. The Pout gets better just before compression due to the better impedance match. Your match is pretty narrow band, don't forget, so a small change in an impedance will have a big effect.
Also, (for theoretical nerds) matching networks for low impedance devices are much more "touchy" than you might think, because of the properties of the bilinear transform. That means that being just a little off when you are at the edge of the smith chart means you will be very far off when you try to match to the center.
I don't have Cadance. I tried sigle point HB just now and the result is just the same. I think HB sweep is just a combination of many sigle point simulation. Basically they use the same algorithm.
I don't get your point. I use the defaul setting for simulation and never intend to make it strict.
Yes, I understand that. But basically they have not much difference. The point is what is the cause of the stability degradation and how to solve it.
Thanks. Actually I am working on the bias circuit now. It is not easy as you said. I am looking for practical and proven designs. Can you give me some suggestion?
Get the stabilty circles and put them here.And obtain them to 10x the frequency that you use. Then we can decide that the problem comes from modelization or design...
Here you are. Left graph is before matching and the right one is after matching. The scale of the smith chart is 2. The black circle is the unity boundary.
I think the key point is not a small S12. What we expect from the simulation result is a S12 as small as possible, though, as you said, it will be degrade significantly in the real world. The important things are:
1. Up to what frequency should we ensure the circuit stable? (normally I give a freq value 10 times as the operation freq)
