questions about LNA layout & test

i'm a beginner in RF layout, could anyone give me some advices about layout in high frequency, what's the extraordinary improtant areas? Or introduce some books about it?

I designed a LNA, I heard that when test the chip, bondwire will bring inductor. when i simulate the LNA, the NF will degrade obviously once i add a inductor in VSS and VDD, while NF will improve if inductor added in input and output pin. I wonder what's the reason and how to avoid it?
Thanks.

would y please show your LNA circuit, i can help y!

thanks for your reply.
The circuit is from JSSC pp. 275-282, 2004.