how to bias VCO
I am designing a CMOS LC VCO at 5GHz. The VCO is powered by 1.8V. And I biased the gate voltage of tail current transistor directly using a power supply(say 1.1V). When the chip come back, the measurement shows it can oscillate at right frequency but the phase noise performance is pretty poor. The 1MHz offset has a PN of -70dBc/Hz, while the simulation gives almost -130dBc/Hz. I guess it's a problem with the biasing. Then I re-simulated the VCO again in ADS with a 1uV V_Noise componenet in series with each power supplies, and it shows a 1MHz PN performance of around -70dBc/Hz. I want to know how the VCO is biasing ususally? Do I need to build a biasing network and using current mirror structure? Is there any useful link for a quick review? Thanks a lot in advance!
Ed
using the inductor as the feed network and the decouper capacitor is more important too!
Since a VCO is an autonomous device, I preassume the biasing in issue is the open drain buffer interface of the VCO, if I'm right, I had used a BGR circuit to bias the buffer.
Rgds
Your VCO's PSRR is too poor.
You can not directly bias the N-tail device by connecting it to power, instead, you need a Bandgap to bias it.
I am sorry to say that you chip will never work well. I guess there is no way to save it other than tape it out again...
Hi, sapphire
We tape-out LC VCO without BangGap biasing circuit and we have no problem with the phase noise. However, we use current mirrors instead of direct voltage bias.
If it is ready the biasing problem, try using a dry-cell battery to bias the VCO, it is much more stable & cleaner than the power supply.
cheers.