How to exlapin constant phase offset when PLL is locked ?

I have a PLL transient simulation. When PLL is very likely locked,i.e.,loop filter voltage has less than 1mV ripple and after >10us settling. But look at the charge pump up/down current pulse I found there is a constant phase error(about the same big as the PFD delay chain's delay time) between the Fref and Fdiv.

My charge pump has good Iup and Idown current match, say maximum 2uA mismatch with a nominal 200uA charge pump current. I donot believe this small mismatch current will cause that big phase offset. Are there other possible reasons to explain this and to avoid this?

Thanks.