How to calculate the settling time of VCO?

I would simulate the vco by injection of an current impulse in the range of pico-amps (almost noise) and see how long it takes to reach steady state oscillation amplitude.
Hope that helps.

Well, that is a way of simulation. What I meant is, is there a rigor analysis existing on this topic?

sorry, not aware of any offhand.

For example, if you using direct phase modulation on VCO, then this settling time will effect the modulation spectrum. Thus this settling time is equivalent to modulation bandwidth this VCO can handle. So How to accurately model this settling time in simulation, how to measure it is of a lot of interesting. Even though normally VCOs in CMOS with loaded Q is small, therefore results a fast settling. But it is not clear to me how to model it. Help please! Thanks.