what is wrong with my code?

i am newbie in verilog and just dont know what is wrong with my code.
this is the crazy simple question:

Develop a Verilog model for a thermostat that has two 8-bit unsigned binary inputs representing the target temperature and the actual temperature in degrees Fahrenheit (˚F). Assume that both temperatures are above freezing (32˚F). The detector has two outputs: one to turn a heater on when the actual temperature is more than 5˚F below target, and one to turn a cooler onwhen the actual temperature is more than 5˚F above target.

and this is my code:

module*C2*(switch,clk,heater_on,cooler_on,enable_a ctual,enable_target);


input clk;
input enable_actual,enable_target;
input*[7:0]*switch*;
reg [7:0]*actual,target;
output* heater_on,*cooler_on;

always @(posedge clk)
begin
if (enable_actual) actual <= switch;

else if (enable_target) target <= switch;

end

assign*heater_on*=*actual*<*target*-*5;
assign*cooler_on*=*actual*>*target*+*5;

endmodule

it didnt show error during compilation.the problem is that the output which are heater_on and cooler_on didnt turn on correctly.what is wrong with my code?can somebody pls help me.

picture2 is the simulation when i want the output heater on to be on.
picture4 is the simulation when i want the output cooler on to be on.

but the simulation was not what i expected for:help pls

The code is O.K., but the simulation stimulus isn't reasonable. You don't manage to set actual and target as intended.

what do u mean?what should i do then?

The switch input must be hold while enable_actual respectively enable_target are active.

thank you so much..i think i get what u mean..