ICC CTS 分频时钟不能插入时钟buffer/inverter

ICC 时钟树综合的时候，design里面有主时钟clk和4分频时钟 clk_div4 两个时钟，
report_clock的时候也正确，运行clock_opt -fix_hold_all_clocks -inter_clock_balance -no_clock_rout的时候有个error,
Cannot process hierarchical clock source 'top_unit_div4_unit/clk_div4' of clock ' top_unit/div4_unit/clk_div4'. (CTS-380).
后面也把clk_div4跳过了，skipping top_unit_div4_unit/clk_div4.......

显示插入时钟树成功了，但clkbuf/inv count 数目是0个，所以就是没有插入buffer或inverter....

那个error是什么原因? 请问这个怎么解决?

感激不尽！

在ICC里面man CTS-380看看

CTS-380 (Error) Cannot process hierarchical clock source ’%s’
of clock ’%s’.
DESCRIPTION
When a clock source is declared on a logical hierarchy port, it is required that
that port be driven by a physical cell -- such as a buffer or clock gate. If the
hierarchical port is undriven, it is not possible to properly process the fanout
clock tree. Optimization of the tree will be skipped.
WHAT NEXT
Modify your netlist to ensure that the hierarchy port has a cell driving it
这是man出来的描述，但我不明白port be driven by a physical cell， 这是为什么呢，我只是一个4分频的输出啊，怎么解决呢?

Modify your netlist to ensure that the hierarchy port has a cell driving it将clkd_div4描述到具体的门级的输出上。

create_clock clkd_div4 到physical cell pin上

thanks for the info

检查你的sdc，时钟可能在逻辑pin上不在物理pin上，看上去是约束造成的