DC保存网表时，出现如下警告，是否可以忽略

Warning: Verilog 'assign' or 'tran' statements are written out. (VO-4)

Warning: Verilog writer has added 6 nets to module CIC_recursive using SYNOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make the correct changes before invoking the verilog writer.(VO-11)

Warning: Verilog writer has added 94 nets to module Compensator using SYNOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make the correct changes before invoking the verilog writer.(VO-11)

Warning: Verilog writer has added 83 nets to module Halfband using SYNOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make the correct changes before invoking the verilog writer.(VO-11)

Warning: Verilog writer has added 7 nets to module Digital using SYNOPSYS_UNCONNECTED_ as prefix.Please use the change_names command to make the correct changes before invoking the verilog writer.(VO-11)

执行change_names -hierarchy -rules Verilog和set verilogout_no_tri true再保存网表，警告依旧没变，而且在执行set verilogout_no_tri true再保存网表，其中三态连线声明tri并没有变成wire型，而是被删除了。这些警告是否有问题?是否可以忽略

第一个警告最好消掉，因为虽然对你的功能没有影响但是对后端apr会有影响，可能后端会不识别；第二个警告你要先确定你功能有没有被改动

对于第一个警告，我在compile之前执行了set verilogout_no_tri true和set_fix_multiple_port_nets -all -buffer_constants，综合之后保存网表，警告依旧存在，唯一与不执行以上两句指令不同的是，在变量声明时tri XX不存在了，并不是向书上说的变成了wire XX。您说会对PR有影响，请问是读入网表时会出现什么错误或warning吗?