IC compiler route not cover pinsing
时间：10-02
整理：3721RD
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I used M2 pins in in design planning stage, or floor planning stage:- resetn + NET resetn
+ DIRECTION input
+ PORT
+ LAYER M2 ( 0 0 ) ( 70 70 )
+ PLACED ( 735.00 0.00 ) N ;
then finished everything for tsmc 28nm node place and route in IC compiler.
but I noticed, in the finished database,that most often than not, the M2 metal would not cover the M2 pin
which is a 0.07X0.07 square.
Since I use M2 label, (M2, pin) to label the center of the pin, the problem would cause the unattached label, and fails LVS in
calibre run.
Please help
+ DIRECTION input
+ PORT
+ LAYER M2 ( 0 0 ) ( 70 70 )
+ PLACED ( 735.00 0.00 ) N ;
then finished everything for tsmc 28nm node place and route in IC compiler.
but I noticed, in the finished database,that most often than not, the M2 metal would not cover the M2 pin
which is a 0.07X0.07 square.
Since I use M2 label, (M2, pin) to label the center of the pin, the problem would cause the unattached label, and fails LVS in
calibre run.
Please help
maybe the boundary constraints has caused this .
besides , M2 pin is too low layer
thank you, yangzai1236, for the reply. I will try those.one question: why IC compiler did not output gds with my original pin shape M2 (0 0) (70 70)?
the strange things are that not every case outputing the same way.