IC compiler P and R not DRC clean

ICC reports DRC clean for tsmc 28nm tech node, but calibre run in cadence still generated a lot of DRC errors.here are summary
RULECHECK G.4:M2i ........................................ TOTAL Result Count = 30(30)
RULECHECK PO.W.20__PO.S.44 ............................... TOTAL Result Count = 124 (124)
RULECHECK M2.W.1 ......................................... TOTAL Result Count = 10(10)
RULECHECK M2.W.4 ......................................... TOTAL Result Count = 10(10)
RULECHECK M2.S.7 ......................................... TOTAL Result Count = 208 (208)
RULECHECK M2.S.8 ......................................... TOTAL Result Count = 22(22)
RULECHECK M2.S.12 ........................................ TOTAL Result Count = 43(43)
RULECHECK M2.A.2 ......................................... TOTAL Result Count = 177 (177)
RULECHECK M2.A.3 ......................................... TOTAL Result Count = 1(1)

please help,

同问?

ICC用的是tf，calibre用的是foundary提供的runset去check drc的。如果flow正常的话，icc一般正常跑出来的DRC应该接近于甚至要比calibre悲观点。不过从你的结果上看，有几个问题：
1.边边角角的地方可能存在一些filler没插的情况或者是边界上没有endcap；
2.M2.S.7 这个DRC有点多，是不是绕线时，一些setting有问题，比如std cell 出pin相关的设置；分析下改下setting应该就好了；
这两个问题解决了，DRC就很少了。

thank you for your suggestions. In my case, I felt that the M2 spacing errors are from power/ground networking creation. I did use create ring and create straps to build power/ground network, any idea if I missed some necessary steps
Many thanks.