clock gating 时序问题

设计中有clock gating，用的是库里自带的clock gating cell，该cell前后时钟分别为：clk，gclk，其中有vclk与clk的latency是用set_latency_adjustment_options 相连接的，cts之后报timing出现了clock gating cell之前的一条路径的slack问题很严重（-0.19ns),其他路径正常，并且这条路径上clock network delay 在data required time 和 data arrival time 差别很大（0.18,0.48）；求助：出现这样的情况是什么原因引起的，需要怎么去解决，或者是这种带有clock gating的设计在cts或者其他的设计步骤中需要怎么去特别处理?报告如图两图差别为一个用到了-path_type full_clock,一个没用）图挂了，在3L和4L文本贴出报告。

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Startpoint: cup_enable (input port clocked by vclk)
Endpoint: g (gating element for clock clk)
Path Group: REGIN
Path Type: max
PointIncrPath
-----------------------------------------------------------
clock vclk (rise edge)0.000.00
clock network delay (ideal)0.480.48
input external delay0.601.08 f
cup_enable (in)0.011.09 f
icc_clock1958/ZN (LVT_CLKNVHSV12)0.02 *1.11 r
icc_clock1959/ZN (LVT_INVHSV20SR)0.02 *1.13 f
icc_place23/Z (LVT_BUFVHSV48)0.06 *1.19 f
g/E (LVT_CLKLAHAQVHSV4)0.12 *1.31 f
data arrival time1.31
clock clk (fall edge)1.201.20
clk (in)0.001.20 f
CTSLVT_CLKBUFVHSV8RO_G1IP/Z (LVT_CLKBUFVHSV8RO)
0.16 *1.36 f
g/CK (LVT_CLKLAHAQVHSV4)0.02 *1.38 f
clock reconvergence pessimism0.001.38
clock uncertainty-0.181.20
g/CK (LVT_CLKLAHAQVHSV4)0.001.20 f
clock gating setup time-0.071.12
data required time1.12
-----------------------------------------------------------
data required time1.12
data arrival time-1.31
-----------------------------------------------------------
slack (VIOLATED)-0.19

Startpoint: cup_enable (input port clocked by vclk)
Endpoint: g (gating element for clock clk)
Path Group: REGIN
Path Type: max
PointFanoutCapTransIncrPath
-------------------------------------------------------------------------------
clock vclk (rise edge)0.000.00
clock network delay (ideal)0.480.48
input external delay0.601.08 f
cup_enable (in)0.030.011.09 f
cup_enable (net)10.010.001.09 f
icc_clock1958/I (LVT_CLKNVHSV12)0.030.00 *1.09 f
icc_clock1958/ZN (LVT_CLKNVHSV12)0.030.021.11 r
n4853 (net)10.020.001.11 r
icc_clock1959/I (LVT_INVHSV20SR)0.030.00 *1.11 r
icc_clock1959/ZN (LVT_INVHSV20SR)0.020.021.13 f
n6 (net)20.040.001.13 f
icc_place23/I (LVT_BUFVHSV48)0.020.00 *1.14 f
icc_place23/Z (LVT_BUFVHSV48)0.040.051.19 f
n26 (net)50.190.001.19 f
g/E (LVT_CLKLAHAQVHSV4)0.200.12 *1.31 f
data arrival time1.31
clock clk (fall edge)1.201.20
clock network delay (propagated)0.181.38
clock reconvergence pessimism0.001.38
clock uncertainty-0.181.20
g/CK (LVT_CLKLAHAQVHSV4)0.001.20 f
clock gating setup time-0.071.12
data required time1.12
-------------------------------------------------------------------------------
data required time1.12
data arrival time-1.31
-------------------------------------------------------------------------------
slack (VIOLATED)-0.19

报告已贴出，在3楼和4楼

vclk 的 clock network delay 不合理

是的，其他路径的都在0.48左右，唯独这条clock gating cell 前的路径只有0.18，我也是头一次做clock gating的东西，造成这种现象的可能原因，还望小编指点

写错了，应该是vclk，那个clock network delay 在CTS前后 要做调整，一般是与clk的latency相同

有的，用set_latency_adjustment_options 调整过

从report上看，显然不合理，如果你认为调整过的latency是对的话，就调input delay

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