分享2个职位，30万左右年薪：PR 以及 PV
Staff Physical Design Engineer 2
Responsibilities:
Responsible for driving and executing the backend methodology from product inception through tapeout including block and chip-level floor planning, placement, scan-reordering, clock tree synthesis, in-place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs) and DRC/LVS/DFM checks.
Define and evolve backend low-power design methodology in 40nm technology to support aggressive low-power techniques for chips having multiple power-domains and dynamic voltage-scaling.
Automate, improve and maintain implementation methods making physical design cycle predictable and keep abreast with industry trends/tools and methodologies.
Integrate of analog and RF-macros using their library models and closing timing at the interface level.
Provide technical direction, mentoring and enhance skills within the physical design team.
Interface with Design and Program Managers to define schedule,resource requirements and track backend schedule.
Qualifications:
Strong background of deep sub-micron CMOS IC physical design including Floor planning, P&R, CTS, IR Drop Analysis, extraction, timing closure with Signal Integrity.
Proven track records of leading multiple product tapeouts with at least one use low-power methodology having multi-VDD or switchable voltage-domains.
Vast experience identifying and resolving physical implementation issues related to Congestion, Routing & Timing Closure (including Crosstalk)
Hands on experience and detailed knowledge of Synopsys (preferred), Cadence or Magma Physical Design-tools.
Expertise in scripting languages like PERL, TCL, AWK, shell, etc. Must be a team player with excellent verbal and written communication skill.
8+ years of direct experience on physical design (MS 6+ years)
第二个：
Staff Physical Verification Engineer1
Responsibilities:
Assist multiple XX design groups in physical verification (DRC/LVS/ERC/Antenna), chip-level layout and tapeout reviews, as well as maintaining physical verification flow, layout and add-on tools. You also will take physical design (P&R) projects from time to time.
Qualifications:
Expert user of Cadence Virtusso, Laker or Mentor IC-Station.
Expert user of Mentor*s Calibre or Synopsys* Hercules runsets or ruledecks creation and debugging.
Must be programming-minded capable of writing Tcl or Perl.
In-depth understanding of fabrication processing steps used in major foundries.
Proven track records of working independently on running and debugging chip-level DRC/LVS/ERC/Antenna results.
Self-motivated team worker, good verbal and written communication skills.
Knowledge of Synopsys Place-and-Route tools
Must able to work under tapeout pressure and tight schedule
8+ years of direct experience on IC layout, physical verification and tapeout (MS 6+years)
good position，so good ,but i can not.
没关系，还有很多其他层次的职位。
有兴趣的给我发email：YestinAi@gmail.com
谢谢，将来有机会再说了。
对刚刚进公司学习pr的我，这要求也太高了
这是咱的奋斗目标呀！
表示羡慕的说！
要求也太高了！
可望不可即啊
只是要求而已，真正符合的，应该已是group mgr或至少年薪不少于30万了。这个级别的人，不会为了小于5万的增长而跳槽的。 所以，难啊
要求好高啊，不过要努力变成这样的人
对刚刚进公司学习pr的我，这要求也太高了
which company?
is it AMD?
No,
If you think it's attractive, please contact me with email: yestinAi@gmail.com
另外一并回了之前的回复：
to 新人： 多跳槽，安安稳稳长不了薪。老实说后端的技术，嘿嘿，专心每天干12小时的话，2年后进展就会非常慢，所以，钱永远都不是用能力来衡量的。（可能有些后端leader不爱听，哈哈）
to 老人：据我所知，目前够资格拿这个薪水的人很多，只是有个现象很奇怪，他们往往期望值会比这个能给的数目高30%，但是目前薪水比这个能给的数目起码差30%。
其实一句话：永远别寄希望于未来，因为你的现在就决定你的未来，只要你现在薪水能前进一步，那你的未来也只会更好。
这是一个搞IC 7年的人的一点忠告。
不过有资格那这个薪水的比这个低30%的不多。期望确实比这高20%以上
收实习吗?
对刚刚进公司学习pr的这个是要求高点,学习！
弱弱的问下：在那里/
LSI , at ShangHai
haooooooooooooooooooooooooo
谢谢分享，谢谢分享
恩，好工作啊！
明显也是奋斗目标
8+ years of direct experience on physical design (MS 6+ years)
这一条99%的人都被干死了，哈哈，算下来要2003年就开始做p&R，那时候，国内有几个人?
HAO~`
职位不错，就是需要6年以上经验